[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Synopsys jobs](https://jobs.opennash.com/companies/synopsys/) · [Search jobs](/search/) Synopsys · Moreira, Portugal # ASIC Digital Design, Staff Engineer Moreira, Portugal Senior individual contributor Design Listed on Synopsys’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/moreira/asic-digital-design-staff-engineer/44408/101134959648) [OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / ASIC Digital Design, Staff Engineer ## Job description We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months. You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward. At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be. ### What You'll Be Doing - Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks - Participate in architecture exploration and contribute to design specifications that guide both implementation and verification - Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets - Support DFT and ATPG flows and coverage analysis ### Generate high quality documents targeting different audiences - customer consumable and to support design implementation and verification teams. - Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps - Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality The Impact You Will Have - Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications - The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams - Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness - The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon - Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays - The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects - Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site ### What You'll Need - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field - At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows - Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling. - Solid understanding of DFT and ATPG methodologies - Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment - Fluency in English, both written and spoken, for documentation and cross-site collaboration - Experience with high-speed memory interfaces such as DDR/HBM is a strong plus ### Who You Are - You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently - When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause - You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab - You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings - You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification The Team You'll Be Part Of You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Moreira, Portugal[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/moreira/asic-digital-design-staff-engineer/44408/101134959648) ## More jobs at Synopsys ### [ASIC Digital Design, Principal Engineer](https://jobs.opennash.com/companies/synopsys/jobs/f19c1f73ebc125f2ffbc/) Moreira, Portugal ### [ASIC Digital Design, Sr Staff Engineer](https://jobs.opennash.com/companies/synopsys/jobs/91bf43e6ba2012a21fc0/) Moreira, Portugal ### [Analog Design, Staff Engineer](https://jobs.opennash.com/companies/synopsys/jobs/e6c2a8c782e9b2fa097e/) Moreira, Portugal ## Similar jobs at other companies ### [ASIC/FPGA Design Verification Engineer, Sr Staff](https://jobs.opennash.com/companies/qualcomm/jobs/69d6f3cd57809dabf76d/) Qualcomm · Ottawa, Ontario, Canada ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Staff ASIC Digital Engineer (SOC Verification, PCIe) with 8 to 12 years of experience](https://jobs.opennash.com/companies/sandisk/jobs/3d2b2a850dec23a8b655/) Sandisk ### [Staff / Senior Staff Engineer - Digital Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/16d277ec1859b13452ff/) Infineon Technologies · Singapore ### [Digital Design Verification Engineer, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/a645ad2a0d00db966bb8/) Qualcomm · Toronto, Ontario, Canada [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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