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Synopsys · Da Nang, Vietnam

# Technical Engineering Intern - Design Verification Internship

Da Nang, Vietnam Early career Design 

Listed on Synopsys’s official careers site. Listed as of November 1, 2026. Check that it is still open and apply there.
[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/da-nang/technical-engineering-intern-design-verification-internship/44408/102314761696)

[OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / Technical Engineering Intern - Design Verification Internship

## Job description

Technical Engineering Intern - Design Verification Internship Introduction We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

### Internship Experience

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Join us and start shaping your future today!

### Mission Statement

Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

### What You'll Be Doing

As a Design Verification Intern, you will play an important role in supporting the development of high-quality semiconductor IP and EDA solutions by assisting with the verification of complex digital designs. The core purpose of this team is to ensure the quality, functionality, and reliability of advanced semiconductor IP and SoC solutions through comprehensive design verification.

Your responsibilities will include:

### Developing and Executing Verification Testcases
- Create comprehensive testcases using SystemVerilog and UVM methodologies to verify complex digital designs, including constrained-random testing scenarios and functional coverage analysis.

### Simulation and Debugging
- Run simulations using industry-standard EDA tools, analyze results, and debug design issues to identify and resolve functional problems, contributing to improved product quality and reliability.

### Testbench Development
- Assist in building and enhancing verification environments and testbenches, implementing verification IP (VIP) for various protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, and other industry-standard interfaces.

### Coverage-Driven Verification
- Develop functional coverage models and analyze coverage metrics to ensure comprehensive verification of design features, helping to reduce design risk and accelerate project execution.

### Collaboration and Learning
- Work closely with design, verification, and validation teams to understand product architecture, verification flows, and methodologies, while contributing fresh perspectives and innovative solutions to technical challenges.

### What You'll Need

Required Qualifications:
- Currently pursuing a degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related technical discipline.
- Basic understanding of Digital Design fundamentals, including combinational/sequential logic, finite state machines (FSM), clocking, and reset concepts.
- Knowledge of Verilog/SystemVerilog for RTL design and verification.
- Familiarity with design verification methodologies, preferably UVM (Universal Verification Methodology) concepts.
- Understanding of verification techniques such as testcase development, constrained-random testing, functional coverage, and debugging.
- Familiarity with Linux/Unix operating environments and simulation tools.
- Strong analytical and problem-solving skills with the ability to investigate and debug complex technical issues.
- Good communication skills, both written and verbal, to effectively collaborate with design, verification, and validation teams.
- Ability to work independently as well as in a team-oriented environment.

### Preferred Qualifications
- Experience with assertion-based verification (SVA) and coverage-driven verification techniques.
- Knowledge of scripting languages such as Python, Perl, Shell, or TCL.
- Familiarity with version control systems like Git.
- Understanding of industry-standard protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, SPI, I2C, or UART.
- Experience with FPGA or hardware verification projects.

### Key Program Facts Program Length

December 2026 – May 2027 (6 months)

### Location

Vietnam (VN10)

### Working Model

Onsite Full-Time/Part-Time: Full-Time Start Date: December 2026 Equal Opportunity Statement Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer.

We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 25, 2026
- Last checked: Nov 1, 2026
- Listed for: 7 days
- Location: Da Nang, Vietnam[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/da-nang/technical-engineering-intern-design-verification-internship/44408/102314761696)

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