[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Synopsys jobs](https://jobs.opennash.com/companies/synopsys/) · [Search jobs](/search/) Synopsys · Markham, Canada # ASIC Digital Design, Principal Engineer Markham, Canada Senior individual contributor Design Listed on Synopsys’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/markham/asic-digital-design-principal-engineer/44408/101594460272) [OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / ASIC Digital Design, Principal Engineer ## Job description ### We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. ### You Are You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams—architecture, verification, physical implementation, and firmware—to deliver industry-leading SERDES PHY IP solutions. Your leadership style is empowering, fostering growth and development within your team, and you’re committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and powers target while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you’re excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you. ### What You’ll Be Doing Leading a diverse team of design engineering the development of next-generation SERDES PHY IP solutions. Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products. Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support. Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles. Mentoring and developing team members, fostering technical growth, and a culture of innovation. Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges. ### The Impact You Will Have Delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency. Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications. Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market. Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance. Enhancing product quality and reliability through rigorous design and verification processes/Flows. Facilitating successful customer adoption and satisfaction through expert support and problem-solving. ### What You’ll Need Bachelor’s degree or higher in Electrical Engineering, with 15 +years of complex technical development experience. Minimum 2 years’ experience in people management and employee development. Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation. ### Strong background in front-end design flows Linting, synthesis, static timing analysis (STA),CDC/RDC, DFT, and power optimization. Excellent communication skills and the ability to work independently and collaboratively. Understanding the PCIe and Ethernet standard is a plus. ### Who You Are Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure. Strong problem-solver with a strategic, analytical mindset. Inspirational leader who motivates and develops technical talent. Collaborative team players who excels in cross-functional environments. Effective communicator who can translate complex technical concepts to diverse audiences. ### The Team You’ll Be A Part Of You’ll join the Synopsys SERDES PHY IP team—a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design. ### Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #LI-NK4 ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Markham, Canada[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/markham/asic-digital-design-principal-engineer/44408/101594460272) ## More jobs at Synopsys ### [Analog Design, Principal Engineer- 18339](https://jobs.opennash.com/companies/synopsys/jobs/2611638b32cd53135ff2/) Markham, Canada ### [Principal Physical Design Methodology Engineer](https://jobs.opennash.com/companies/synopsys/jobs/f3fca4da31c854262bf7/) Markham, Canada ### [Sr Staff PCB Design Engineer](https://jobs.opennash.com/companies/synopsys/jobs/362b1067755478d9007c/) Markham, Canada ### [Silicon IP Program Manager - 18404](https://jobs.opennash.com/companies/synopsys/jobs/55fc850b9e0a487f4f4b/) Markham, Canada ### [Silicon IP Program Manager - 18405](https://jobs.opennash.com/companies/synopsys/jobs/319d13cc8e50f214efaa/) Markham, Canada ## Similar jobs at other companies ### [ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs | 12-16 Years | Pune/ Bangalore)](https://jobs.opennash.com/companies/cisco-systems/jobs/db2ada12bdafe15956a6/) Cisco Systems · Pune, India ### [Sr. Lead ASIC design Engineer - Digital Design](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/6c6b694c70bacc9a74f5/) NXP Semiconductors · Hyderabad ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [ASIC/FPGA Design Verification Engineer, Senior](https://jobs.opennash.com/companies/qualcomm/jobs/f7cc8fb7b0460376d7d6/) Qualcomm · Ottawa, Ontario, Canada ### [Staff ASIC Digital Engineer (SOC Verification, PCIe) with 8 to 12 years of experience](https://jobs.opennash.com/companies/sandisk/jobs/3d2b2a850dec23a8b655/) Sandisk [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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