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Synopsys · Ho Chi Minh City, Vietnam

# Technical Engineering Intern - Design for Test (DFT) Internship

Ho Chi Minh City, Vietnam Early career Design 

Listed on Synopsys’s official careers site. Listed as of November 1, 2026. Check that it is still open and apply there.
[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/ho-chi-minh-city/technical-engineering-intern-design-for-test-dft-internship/44408/102251697392)

[OpenNash Jobs](https://jobs.opennash.com/) / [Synopsys](https://jobs.opennash.com/companies/synopsys/) / Technical Engineering Intern - Design for Test (DFT) Internship

## Job description

Technical Engineering Intern - Design for Test (DFT)

### Internship Introduction We Are

Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

### Internship Experience

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Join us and start shaping your future today!

### Mission Statement

Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

### What You'll Be Doing

As a DFT Intern Engineer, you will contribute to the development of high-quality semiconductor IP and SoC solutions while gaining invaluable hands-on experience in real-world chip development projects.

Your responsibilities will include:

### Supporting DFT Implementation and Verification
- Assist in Design-for-Test activities including scan insertion, ATPG (Automatic Test Pattern Generation), test coverage analysis, and validation to ensure silicon testability and quality.

### Developing Automation Solutions
- Create and deliver scripting and automation tools using TCL, Perl, Python, or Shell to improve engineering productivity and streamline DFT workflows.

### Collaborating on Chip Development Projects
- Work alongside experienced engineers on innovative technologies powering data center, AI, mobile, and automotive applications, contributing to the successful delivery of trusted silicon solutions.

### Debugging and Problem-Solving
- Analyze and resolve design and test-related issues, applying strong analytical skills to enhance design efficiency and manufacturing yield.

### Participating in Technical Reviews
- Engage actively in team discussions, technical reviews, and project activities, sharing your ideas and learning from industry experts in semiconductor design and test methodologies.

### What You'll Need

Required Qualifications:
- Currently pursuing a final-year undergraduate or graduate degree in Electronics Engineering, Computer Engineering, Telecommunications, Electrical Engineering, or related disciplines.
- Basic understanding of CMOS and digital logic design fundamentals.
- Scripting experience with languages such as TCL, Perl, Python, or Shell.
- Strong analytical and problem-solving skills with a passion for semiconductor technologies.
- Good communication skills in English, both written and verbal.
- Self-motivated, eager to learn, with strong teamwork and collaboration abilities.

### Preferred Qualifications
- Basic knowledge of Design-for-Test (DFT) concepts, including Scan, ATPG, and JTAG.
- Familiarity with Linux/Unix environments.
- Experience with EDA tools such as Synopsys Design Compiler (DC), Fusion Compiler (FC), PrimeTime, TestMax, Verdi, or similar platforms.
- Participation in academic, research, or personal projects related to digital IC design or ASIC design.

### Key Program Facts Program Length

December 2026 – May 2027 (6 months)

### Location

Ho Chi Minh (VN07)

### Working Model

Onsite Full-Time/Part-Time: Full-Time Start Date: December 2026 Equal Opportunity Statement Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer.

We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 25, 2026
- Last checked: Nov 1, 2026
- Listed for: 7 days
- Location: Ho Chi Minh City, Vietnam[Apply on Synopsys’s careers site →](https://careers.synopsys.com/job/ho-chi-minh-city/technical-engineering-intern-design-for-test-dft-internship/44408/102251697392)

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