[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Austin, TX # Principal FPGA Emulation Engineer Austin, TX, United States Full-time Senior individual contributor Operations Listed on Renesas Electronics’s official careers site. Posted September 25, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000151949089-principal-fpga-emulation-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Principal FPGA Emulation Engineer ## Job description About the Role Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon — proving out control loops, catching RTL issues early, and de-risking tape-out. These FPGA platforms are emulation vehicles, not production hardware. Success is measured by how faithfully and how fast they reproduce the target silicon: functional equivalence to the golden ASIC RTL, real-time (or near-real-time) performance for closed-loop power and DSP validation, and deep visibility for pre-silicon debug. ### What You'll Do Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA — advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform. Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design — handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and stubbing or modeling of analog/mixed-signal blocks. Map designs onto the FPGA fabric to fit and to hit emulation speed — steering resource inference (DSP/multiplier slices, block vs. distributed memory), clocking, and pipelining so the design achieves the real-time performance the validation requires. ### Build the real-time environment around the digital core model or interface to the analog and power stages (ADC/DAC/PWM, gate drivers, plant/converter models), including hardware-in-the-loop with real or emulated power hardware where needed. Develop deep pre-silicon debug and visibility — logic analysis, long-run waveform capture, triggering, and assertions — and enable firmware/software co-development ahead of silicon. Define and continuously improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python). ### Provide technical leadership mentor engineers, lead reviews, and drive emulation and tooling decisions across the silicon and systems teams. ## Qualifications ### Required Qualifications Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs. Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL. Deep understanding of FPGA internal architecture and primitives — DSP/multiplier slices, block and distributed RAM, carry chains, and clocking — and a proven ability to map designs onto these resources to fit large ASIC RTL and reach real-time emulation performance (memory/SRAM macro mapping, DSP inference, clock-enable conversion, control-set and fanout management). ### Hands-on experience adapting ASIC RTL for FPGA clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling. Strong command of the full FPGA implementation flow — synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) — on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus. ### Hardware bring-up and debug experience in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug. Proficiency scripting for automation (TCL, Python). Demonstrated technical leadership — mentoring, reviews, and driving cross-team technical decisions. BS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience). ### Preferred Qualifications Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models). Understanding of digital power-conversion control and mixed-signal systems — converter topologies, control loops, PWM/PFM, and magnetics — to build faithful models and validate power-control architectures. FPGA DSP implementation and real-time emulation of DSP datapaths: FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, including high-throughput techniques such as folding/unfolding. Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce. Model-based design with Simulink and/or Xilinx System Generator. ### High-speed interface experience JESD204B, PCIe, 1G/10G Ethernet, Aurora. ASIC design or tape-out exposure, including DFT/scan considerations in emulation. Ability to architect and build a custom in-house FPGA prototyping platform — board architecture, high-speed PCB design, signal integrity, and bring-up — a plus as we may develop our own hardware in the future. Embedded/microcontroller and firmware co-development experience (C/assembly); MATLAB, C/C++. ## At a glance - Posted by the employer: Sep 25, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 24 days - Location: Austin, TX, United States - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000151949089-principal-fpga-emulation-engineer) ## More jobs at Renesas Electronics ### [Senior Manager Analog Engineering](https://jobs.opennash.com/companies/renesas-electronics/jobs/882b8c2fda5b2593acaf/) Austin, TX, United States ### [Physical Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/9d397a8741322c02392e/) Austin, TX, United States ### [Principal Package Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/7b54cdd0b091c856232f/) Austin, TX, United States ### [Project/Program Design Senior Manager](https://jobs.opennash.com/companies/renesas-electronics/jobs/4b9bcd141f221fb78af0/) Austin, TX, United States ### [(Senior) Layout Engineer (f/m/d)](https://jobs.opennash.com/companies/renesas-electronics/jobs/23ca87c951bb3149680f/) Bingen, Germany ## Similar jobs at other companies ### [SoC Systems & Infrastructure Engineer (Design • Validation • Debug • FPGA • Emulation • Software)](https://jobs.opennash.com/companies/qualcomm/jobs/7f9d809aa1a5371078bb/) Qualcomm · San Diego, California, United States of America ### [Emulation Engineer / Emulation Platform Engineer -Senior](https://jobs.opennash.com/companies/qualcomm/jobs/b56d5e7cc721420c89b0/) Qualcomm · Austin, Texas, United States of America ### [Principal Engineer Digital FPGA/Sr. Principal Engineer Digital FPGA (Level 3/4)](https://jobs.opennash.com/companies/northrop-grumman/jobs/9b79263e99c50a4aceb1/) Northrop Grumman · United States-California-Manhattan Beach ### [FPGA Engineer Lead](https://jobs.opennash.com/companies/lockheed-martin/jobs/105b79576b8544ebe781/) Lockheed Martin · Orlando, FL ### [Intern Engineer - FPGA](https://jobs.opennash.com/companies/general-dynamics/jobs/91da666be7d29f499ae9/) General Dynamics · Bloomington, MN, US [Jobs in Austin, TX](/locations/us/tx/austin/)[Jobs in Texas](/locations/us-tx/)[Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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