[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/)

Renesas Electronics · Noida, India

# Staff/ Sr Staff Engineer, Physical Design

Noida, India Full-time Senior individual contributor Design 

Listed on Renesas Electronics’s official careers site. Posted March 7, 2026. Check that it is still open and apply there.
[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000113319407-staff-sr-staff-engineer-physical-design-)

[OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Staff/ Sr Staff Engineer, Physical Design

## Job description

### Experience

7-10 years

### Role Summary

We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams.

### Key Responsibilities

Own RTL synthesis from elaboration to final sign‑off. Develop and debug design constraints and support DFT insertion. Understand Physical design cycle and different handshaking across teams. Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists. Create, maintain, and debug UPF, ensuring alignment with FE power intent. Define and manage power domains (power switches, isolation, retention, always‑on).

Support low‑power sign‑off (VCLP / power checks). Handle RTL ECOs during late design stages. Automate flows using TCL scripting.

## Qualifications

### Required Qualifications

4+ years of hands‑on experience in Physical design for SoC designs. Strong knowledge of RTL, synthesis optimization, and low‑power design. Hands‑on experience with UPF creation and power‑domain modelling. Experience with tools such as Cadence Genus, Synopsys Fusion Compiler, Conformal, VCLP. Strong TCL scripting skills (Perl/Python is a plus). Preferred Advanced node experience (7nm / 5nm or below). Power‑aware ECO experience.

Exposure to physical‑aware synthesis. Ownership of subsystem or SoC‑level UPF.

## At a glance
- Posted by the employer: Mar 7, 2026
- First seen by OpenNash: Oct 12, 2026
- Last checked: Oct 19, 2026
- Listed for: 226 days
- Location: Noida, India
- Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000113319407-staff-sr-staff-engineer-physical-design-)

## More jobs at Renesas Electronics

### [Principal Engineer, RTL Design](https://jobs.opennash.com/companies/renesas-electronics/jobs/4f35d2ce7070101c54c8/)

Noida, India

### [Sr Engineer, Design Enablement](https://jobs.opennash.com/companies/renesas-electronics/jobs/61192da2f271e0e123b1/)

Noida, India

### [Sr Staff /Staff Engineer, RTL Design](https://jobs.opennash.com/companies/renesas-electronics/jobs/dda49782cd1e7793215e/)

Noida, India

### [Manager – Regional Product Marketing, EPMA](https://jobs.opennash.com/companies/renesas-electronics/jobs/7d3a911e0e68db0dc658/)

Noida, India

## Similar jobs at other companies

### [NPU Physical Design Engineer (Lead/Staff/Sr Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/6c197dcc0ecf984e3558/)

Qualcomm · Bangalore, India

### [SoC Physical Design CAD Engineer (Staff/Sr Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/de557e36c083dee95dbc/)

Qualcomm · Bangalore, India

### [Senior Staff Engineer Physical Design and Methodology (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/46bbe226ff31021fb81f/)

Infineon Technologies · Munich

### [Senior Staff/Staff Engineer Metrology](https://jobs.opennash.com/companies/infineon-technologies/jobs/ed0cd97dfd795a5a3a83/)

Infineon Technologies · Kulim

### [Staff Physical Design Engineer - SoC EMIR Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/83d695a914e907abe2aa/)

Astera Labs · Tel Aviv

[Design jobs](/functions/design/)

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)
