[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Kodaira, Japan # HPC SoC Timing Design Engineer/Leader Kodaira, Japan Full-time Design Listed on Renesas Electronics’s official careers site. Posted June 22, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000133301272-hpc-soc-timing-design-engineer-leader) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / HPC SoC Timing Design Engineer/Leader ## Job description 【Reason for Hiring】 High performance SoC are key parts to realize automobile's electric and high performance which are so called CASE (Connected, Automated, Shared, Electric). SoC are becoming more larger and complex to meet the demand of more function and high performance. Cost competition is also a key. In the timing design viewpoint, developing a large scale complex SoC is required, and we want to recruit an innovative engineer. We're waiting for a engineer who can work with global mindset, since we're co-working with Vietnam, India design site (language: English) 【Role Responsibilities】 SoC Timing Design Engineer or Leader. Timing design technology development, and product development by Static Timing Analysis, Timing Constraint design and Logic Synthesis. Static Timing Analysis Timing design by using EDA vendor's EDA tool Timing constraint design Timing constraint design by using EDA vendor's tool and Renesas tool Logic synthesis: Logic Synthesis by using EDA vendor's tool. All Static Timing Analysis, Timing Constraint design and logic synthesis case will be co-working with oversea design center. *The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process. 【What We Offer】 In the PhysicalDesign role, the manager is also deeply involved in the actual design process, leading the execution of product development and improvement of the development flow. This is an important role in the completion of LSI product design from a position close to the design site. The process node used is the most advanced node (3nm) for automotive applications. We are proud that the difficulty and satisfaction of digital backend design is at the top level. We collaborate with overseas EDA vendors and design centers, and you can participate in the work of a global organization. 【 What Are We Looking For 】 Ability to tackle challenges - Strong leadership skills Capability to see the big picture - Ability to propose effective solutions ## Qualifications 【MUST】 Timing design (Static Timing Analysis, Timing Constraint debugging)experience: over 8 year English at a communicative level Jaoanese at a communicative level 【WANT】 Hardware language (ex. Verilog-HDL) Experience of using English in business ## At a glance - Posted by the employer: Jun 22, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 119 days - Location: Kodaira, Japan - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000133301272-hpc-soc-timing-design-engineer-leader) ## More jobs at Renesas Electronics ### [ARM CPU Subsystem Design Leader](https://jobs.opennash.com/companies/renesas-electronics/jobs/860b92d0e84cb63dc206/) Kodaira, Japan ### [Clock and Reset system or PAD design leader for automotive SoC design](https://jobs.opennash.com/companies/renesas-electronics/jobs/8cd76405dfe66f518b6e/) Kodaira, Japan ### [Design Verification Engineer（SoC機能検証エンジニア）(1)](https://jobs.opennash.com/companies/renesas-electronics/jobs/bfada598021e7fff2e81/) Kodaira, Japan ### [Design Verification Engineer（SoC機能検証エンジニア）(2)](https://jobs.opennash.com/companies/renesas-electronics/jobs/7ed0a0aaafa7da94d4a3/) Kodaira, Japan ### [EDA Infrastructure Engineer (Linux / Server & Storage)](https://jobs.opennash.com/companies/renesas-electronics/jobs/acda2277f756f5472e40/) Kodaira, Japan ## Similar jobs at other companies ### [SoC STA/Timing Engineer (Senior Staff/Principal)](https://jobs.opennash.com/companies/qualcomm/jobs/84dd17ebe4cab9226ef2/) Qualcomm · Bangalore, India ### [STA Design Engineer - Static Timing Analysis - Cork, Ireland](https://jobs.opennash.com/companies/qualcomm/jobs/bd7ae4505f66f3e5dbe5/) Qualcomm · Cork, Ireland ### [Internship - Synthesis & Timing/Area RTL Design Analysis (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/853d811521520b2540a8/) Infineon Technologies · Munich ### [Physical Design Engineer, SoC Static Timing Analysis](https://jobs.opennash.com/companies/alphabet/jobs/ac496d8fdfae24904aeb/) Alphabet · Tel Aviv, Israel +1 more ### [Working Student - RTL Design for SoC Fault Tolerance & Error Detection (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/ff06c8b5953ff147853a/) Infineon Technologies · Munich [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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