[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Chandler, AZ # Staff Digital Design Engineer Chandler, Arizona, United States Full-time Senior individual contributor Design Listed on Renesas Electronics’s official careers site. Posted July 16, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000138202470-staff-digital-design-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Staff Digital Design Engineer ## Job description Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications. ### Job Purpose & Dimensions - Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes. - Support full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development. - Provide technical leadership & influence to the digital design team by contributing to technical discussions & reviews, mentoring junior engineers, and supporting recruitment. - Work closely with Analog and Verification engineers to deliver high-quality silicon solutions. ### Responsibilities - Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals. - Designing digital RTL that meets timing, area, power and any adhering standards specifications. - Integrating design at the top level and running block & top-level simulations. - Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF. - Working closely with P&R team to generate a layout that meets timing, area, and power requirements. - Support DFT strategy and implementation, and review test case development. - Assisting with top level test-bench debug, and running RTL & gate level simulations - Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification. - Supporting analog team to develop AMS, System Verilog or Verilog-real behavioral models. - Developing detailed block & chip level design documents and collateral. - Holding and participating in key design reviews and completion of various checklists. - Perform silicon evaluation as required. - Document device errata, develop work-around solutions, implement engineering changes when necessary. ## Qualifications - >10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management. - Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline. - Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. - Strong understanding of ASIC design methodology. - Strong understanding of Lint, CDC & RDC tools. - Strong understanding of block-level & chip-level verification techniques. - Strong & proven ability to debug both RTL & gate-level simulations. - Mandatory competence in written and verbal English. - Willingness to travel domestically or internationally on short notice. - Ability to work independently and collaboratively. ### Preferred - experience with Digital Signal Processing (DSP) concepts and hardware realizations. - experience with methodology and flow automation using appropriate scripting. - experience with mixed-signal design methodologies. - experience developing design constraints and hand-off to P&R. - experience with STA and timing closure. - experience with low-power design techniques, including clock and power gating (UPF). - experience with power analysis and optimization. - experience with advanced verification methodologies (UVM). - experience with industry-standard protocols such as AMBA or I2C. ## At a glance - Posted by the employer: Jul 16, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 95 days - Location: Chandler, Arizona, United States - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000138202470-staff-digital-design-engineer) ## More jobs at Renesas Electronics ### [Director, Digital Design & Verification](https://jobs.opennash.com/companies/renesas-electronics/jobs/07b6572902957a9edec9/) Chandler, Arizona, United States ### [Senior Analog Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/98d5b7d0a5438625e77b/) Chandler, Arizona, United States ### [Senior Staff Analog Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/a7eb5b2aa6d5c301841b/) Chandler, Arizona, United States ### [Staff Analog Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/a46a31d569f0ed5ba8b6/) Chandler, Arizona, United States ### [Principal ESD Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/26224f97c86722b007ba/) Chandler, Arizona, United States ## Similar jobs at other companies ### [Digital & Power Circuit Design Engineer, Sr Staff - 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