[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Kodaira, Japan # ARM CPU Subsystem Design Leader Kodaira, Japan Full-time Design Listed on Renesas Electronics’s official careers site. Posted April 2, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000118372857-arm-cpu-subsystem-design-leader) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / ARM CPU Subsystem Design Leader ## Job description 【Background of the Recruitment】 As vehicles become increasingly electrified and intelligent, automotive SoCs are now positioned as a central technology supporting vehicle performance and functionality. The R-Car series has continued to grow as a large‑scale SoC through the advanced integration of numerous and diverse IPs, including CPU, memory, high‑speed interfaces, AI/video, functional safety, and security. Our organization is responsible not only for in‑house IP development but also for the selection, integration, and implementation of external IPs, making the strengthening of technical leadership in core areas such as the CPU subsystem a key focus. Against this background, we are seeking technical leaders who can define design direction, make sound technical decisions, and move development forward in collaboration with surrounding teams and IP vendors. This role offers an opportunity for engineers who wish to drive development with a strong technical foundation while preparing to take on broader responsibilities in the future. 【Job Description】 Play a key role in specification definition and architectural study of the CPU subsystem for automotive SoCs (R-Car series). Work on the CPU subsystem including CPU cores, cache architecture (L1/L2/L3, cache coherency), and memory-related areas, and organize design directions from a subsystem-level optimization perspective while owning a primary technical area. During logic design and verification phases, identify and structure technical issues, contribute to design decisions, and help drive development forward. Consider constraints such as power, performance, and reliability, and make technical judgments consistent with overall SoC requirements. For integrated third‑party IPs, communicate with IP vendors to confirm specifications, clarify constraints/assumptions, and support issue resolution. Collaborate with design teams in India and Vietnam and with IP vendors, working in English within a global development environment. ※The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process. ## Qualifications 【MUST】 Hands-on experience in at least one of the following areas, including specification study, design, verification, or performance evaluation: - CPU / processor cores (e.g., exceptions, interrupts, control logic) - Cache architecture (e.g., cache hierarchy, coherency, memory consistency) - Memory-related areas (e.g., interconnect, memory control, memory interfaces) Ability to organize design directions and key discussion points based on requirements and share them with stakeholders. Understanding of the logic design and verification flow, and experience actively participating in technical reviews/discussions. Communication skills to collaborate across teams and contribute to technical consensus building. Willingness and ability to communicate in English for technical meetings and specification reviews. 【WANT】 Experience taking a technical lead role at subsystem or IP level (e.g., leading design reviews, guiding technical discussions). Experience with multi-core CPU systems and/or cache coherency mechanisms. Experience in SoC integration involving CPU, cache, and memory-related components. Knowledge of power domain separation and physical implementation considerations (e.g., P&R). Experience in automotive SoC development or design/verification with functional safety or reliability considerations. Experience in technical communication and coordination with overseas sites and/or third‑party IP vendors. Japanese language proficiency at a conversational level ## At a glance - Posted by the employer: Apr 2, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 200 days - Location: Kodaira, Japan - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000118372857-arm-cpu-subsystem-design-leader) ## More jobs at Renesas Electronics ### [Clock and Reset system or PAD design leader for automotive SoC design](https://jobs.opennash.com/companies/renesas-electronics/jobs/8cd76405dfe66f518b6e/) Kodaira, Japan ### [Design Verification Engineer（SoC機能検証エンジニア）(1)](https://jobs.opennash.com/companies/renesas-electronics/jobs/bfada598021e7fff2e81/) Kodaira, Japan ### [Design Verification Engineer（SoC機能検証エンジニア）(2)](https://jobs.opennash.com/companies/renesas-electronics/jobs/7ed0a0aaafa7da94d4a3/) Kodaira, Japan ### [EDA Infrastructure Engineer (Linux / Server & Storage)](https://jobs.opennash.com/companies/renesas-electronics/jobs/acda2277f756f5472e40/) Kodaira, Japan ### [HPC DDR Controller Design Engineer / Leader](https://jobs.opennash.com/companies/renesas-electronics/jobs/8c0c91c833c5b33abf1e/) Kodaira, Japan ## Similar jobs at other companies ### [CPU Staff/Senior Staff Engineer – ARM GIC & CPU Post-Silicon Validation](https://jobs.opennash.com/companies/qualcomm/jobs/2b736a4e97ed2e428565/) Qualcomm · Bangalore, India ### [Design Verification Engineer — Memory Subsystem (Vancouver)](https://jobs.opennash.com/companies/qualcomm/jobs/41aeaaae7a0c3926967d/) Qualcomm · Vancouver, British Columbia, Canada ### [Senior Solutions Architect - ARM CPU](https://jobs.opennash.com/companies/nvidia/jobs/022333a4225465987ede/) NVIDIA · China, Beijing ### [Assistant Relationship Manager (ARM)](https://jobs.opennash.com/companies/citigroup/jobs/862c58af5db6beddefa5/) Citigroup · Sg Singapore ### [〔法金〕大型法人助理客戶關係經理(ARM) (台北)](https://jobs.opennash.com/companies/ts-financial-holding/jobs/ee66a8920eea9a50a166/) TS Financial Holding [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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