[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Austin, TX # Principal Package Design Engineer Austin, TX, United States Full-time Senior individual contributor Design Listed on Renesas Electronics’s official careers site. Posted September 26, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000151981559-principal-package-design-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Principal Package Design Engineer ## Job description ### Principal Package Design Engineer Location Hybrid at main Renesas Electronics America locations (San Jose, CA / Austin, TX) ### Department Semiconductor Power Product Group Reports To: Senior Principal, Device Design Packaging Technology, Strategy, Operations ### Position Summary We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, applications, product engineering, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production. ### Key Responsibilities Lead Advanced Packaging Initiatives: Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging System-in-package (SiP) Ball grid array (BGA/CSP) ### Wafer-to-wafer and die-to-wafer heterogeneous bonding Architecture & Simulation Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on, deep simulation expertise. ### OSAT & Vendor Strategy Drive package technology and OSAT selection and development for new product introductions (NPI). ### Cross-Functional Collaboration Work closely with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure package compatibility and performance. ### Layout & Stack-Up Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy. ### Simulations & Modeling Perform and guide others on simulations and analysis related to: Signal integrity / power integrity Thermal performance Mechanical stress / warpage Design for manufacturability (DFM) ### Assembly & Qualification Develop assembly flows and process requirements for OSATs and manufacturing partners. Lead package qualification activities, including DOE planning, failure analysis, and reliability testing. ### Yield & Issue Resolution Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp. Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization. ### Documentation & Leadership Create and maintain package specifications, design rules, process documentation, and technical reports. Mentor junior engineers and provide technical leadership across packaging initiatives. ## Qualifications ### Required Qualifications Education: MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field. ### Experience 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration. ### Technical Depth Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management. ### Reliability & Tools Deep understanding of thermal, mechanical, and electrical interactions in package design and extensive, hands-on model setup, simulations, and analysis. Strong background in CAD and simulation tools. Experience with package reliability testing and qualification standards. ### Supply Chain Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains. ### Problem Solving & Leadership Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross-functional communication skills. ### Preferred Qualifications Master’s or PhD in a relevant engineering discipline. Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and their applications in consumer, industrial, automotive, and high-performance computing markets. Experience with power products in high-performance computing, AI/ML hardware, or mobile products. Hands-on experience with tools for package design and simulation such as: Cadence Allegro Package Designer SolidWorks ANSYS COMSOL JMP / Minitab Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods. Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging. ### Key Skills Advanced package concept engineering and design Materials selection and development Thermal and mechanical simulations and analysis Failure analysis & reliability engineering - Design for Manufacturability (DFM/DFX) - Process development & supplier collaboration Technical leadership & problem-solving Success in This Role A successful Principal Package Design Engineer will: Deliver robust package solutions that meet performance, reliability, and cost targets. Enable smooth product transfer from concept to development to manufacturing. Reduce packaging risks through strong technical analysis, hands-on simulations, and qualification planning. Improve yield, quality, and manufacturability through collaboration with internal and external partners. Working Conditions May require occasional travel to supplier, OSAT, or design/manufacturing/R&D sites. ## At a glance - Posted by the employer: Sep 26, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 23 days - Location: Austin, TX, United States - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000151981559-principal-package-design-engineer) ## More jobs at Renesas Electronics ### [Physical Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/9d397a8741322c02392e/) Austin, TX, United States ### [Project/Program Design Senior Manager](https://jobs.opennash.com/companies/renesas-electronics/jobs/4b9bcd141f221fb78af0/) Austin, TX, United States ### [Principal FPGA Emulation Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/db6d435f43fe4af0490d/) Austin, TX, United States ### [Senior Manager Analog Engineering](https://jobs.opennash.com/companies/renesas-electronics/jobs/882b8c2fda5b2593acaf/) Austin, TX, United States ### [(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)](https://jobs.opennash.com/companies/renesas-electronics/jobs/030ff65556291fb78d30/) Shanghai, China ## Similar jobs at other companies ### [Package Design Engineer - Staff](https://jobs.opennash.com/companies/qualcomm/jobs/0f92ad829e5462a761ac/) Qualcomm · San Diego, California, United States of America ### [RF Package Design Engineer, Senior Staff](https://jobs.opennash.com/companies/qualcomm/jobs/07cd9efdf636a5e8f171/) Qualcomm · San Diego, California, United States of America ### [Circuit Design Engineer, Principal](https://jobs.opennash.com/companies/lockheed-martin/jobs/78cd34d8da60b7b89600/) Lockheed Martin · Goleta, CA ### [Principal Package Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d243c5dc9a633d35cf49/) Microsoft · United States, Washington, Redmond, California, Mountain View, Texas, Austin, North Carolina, Raleigh, Oregon, Hillsboro ### [Principal Product Design Engineer](https://jobs.opennash.com/companies/comfort-systems-usa/jobs/6973033b0f66ed1f6420/) Comfort Systems USA · Indianapolis, IN OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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