[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Renesas Electronics · Bengaluru, KA, India # Staff/ Senior Staff Engineer, STA Bengaluru, KA, India Full-time Senior individual contributor Operations Listed on Renesas Electronics’s official careers site. Posted October 22, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000157040169-staff-senior-staff-engineer-sta) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Staff/ Senior Staff Engineer, STA ## Job description We are looking for a highly motivated STA Engineer to join our VLSI design team. The ideal candidate will be responsible for driving timing closure and signoff readiness for block-level and full-chip designs across all operating modes and process corners. This role involves developing and validating timing constraints, performing comprehensive timing analysis, and collaborating closely with RTL Design, Synthesis, Clock Tree Synthesis (CTS), and Physical Design teams to identify, debug, and resolve timing violations. The successful candidate will play a key role in achieving timing convergence and delivering high-quality silicon through successful tapeout. This position offers an opportunity to work on advanced semiconductor technologies and contribute to the development of high-performance, power-efficient SoCs. ### What You'll Do Perform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments. Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations. Develop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness. Partner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals. Drive timing closure through ECO implementation, timing optimization, and timing convergence activities. Perform pre-layout and post-layout timing analysis and support tapeout signoff requirements. Analyze timing impact due to process, voltage, and temperature (PVT) variations and variation-aware methodologies. Review and validate timing exceptions including false paths, multicycle paths, case analysis, and clock definitions. Identify root causes of timing violations and recommend effective optimization strategies. Participate in cross-functional design reviews and provide guidance on timing-related issues. Generate timing reports, closure metrics, and signoff summaries for project stakeholders. Support design quality improvements by establishing and enhancing STA methodologies, automation, and best practices. ## Qualifications ### Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field. 7 to 13 years of hands-on experience in Static Timing Analysis (STA) and timing closure for block-level and/or full-chip semiconductor designs. Strong understanding of CMOS fundamentals, timing concepts, and end-to-end semiconductor design flow. Solid experience with setup/hold analysis, path-based analysis (PBA), and timing signoff methodologies. In-depth knowledge of OCV, AOCV, POCV, timing derates, uncertainty modeling, and MMMC analysis. Strong understanding of clock tree concepts including clock latency, skew, jitter, uncertainty, and clock propagation. Experience developing and debugging timing constraints and timing exceptions. Good understanding of SDC syntax, false paths, multicycle paths, generated clocks, and case analysis. Hands-on experience with timing closure techniques and ECO methodologies. Proficiency with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus. Good scripting and automation skills using Tcl, Perl, Python, or similar languages. Strong analytical, debugging, and problem-solving skills with the ability to independently resolve complex timing issues. Excellent communication and collaboration skills in cross-functional engineering environments. ### Preferred Qualifications Experience with low-power timing analysis and UPF/CPF-aware STA methodologies. Familiarity with signal integrity (SI)-aware timing analysis, crosstalk analysis, and IR-drop-aware timing closure. Understanding of advanced technology nodes and variation-aware signoff methodologies. Exposure to automation, flow development, and methodology enhancement. Experience collaborating with Physical Design, RTL, Verification, DFT, and Signoff teams. Knowledge of advanced timing signoff practices for high-performance and low-power SoCs. ## At a glance - Posted by the employer: Oct 22, 2026 - First seen by OpenNash: Oct 26, 2026 - Last checked: Nov 2, 2026 - Listed for: 11 days - Location: Bengaluru, KA, India - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000157040169-staff-senior-staff-engineer-sta) ## Hiring at Renesas Electronics - Open jobs: 774 - New in the last 7 days: After two weekly collections - Tracked since: Oct 12, 2026 [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Renesas Electronics ### [Mgr/Sr Mgr, Analog Engineering](https://jobs.opennash.com/companies/renesas-electronics/jobs/a99b8cde8197efec46c8/) Bengaluru, KA, India ### [Online Field Applications Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/6a79d5885770fe80f8d6/) Bengaluru, KA, India ### [Principal ATE Test Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/06ed631c824b1e42cc47/) Bengaluru, KA, India ### [Principal Analog Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/190558d9457b6d7a3997/) Bengaluru, KA, India ### [Principal DFT Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/24f96046deb8dd22389b/) Bengaluru, KA, India ## Similar jobs at other companies ### [DDR STA/Timing Engineer (Staff/ Senior Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/d2d3adc5a6bb664535cf/) Qualcomm · Bangalore, India ### [STA Staff Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/30e492594f0929797cc1/) Qualcomm · Noida, Uttar Pradesh, India ### [Staff/ Principal Physical Design STA Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/b7a1854ba8448798a208/) Astera Labs · Israel ### [Senior Staff/Staff Engineer Metrology](https://jobs.opennash.com/companies/infineon-technologies/jobs/ed0cd97dfd795a5a3a83/) Infineon Technologies · Kulim ### [Staff / Senior Staff Engineer - Digital Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/16d277ec1859b13452ff/) Infineon Technologies · Singapore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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