[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Tempe, AZ # Staff Package Design Engineer Tempe, Arizona, United States Full-time Senior individual contributor Design Listed on Renesas Electronics’s official careers site. Posted September 30, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000152681758-staff-package-design-engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Staff Package Design Engineer ## Job description In this role, you will work at the intersection of IC design, advanced package development, and system-level implementation. You will play a critical role in designing and delivering next-generation, high-performance semiconductor package solutions, including power modules, chiplet-based architectures, FCBGA, SiP, WLCSP, wire-bonded, QFP, and QFN packages supporting automotive SoCs, industrial IoT microcontrollers, and AI-enabled embedded computing platforms. This role requires strong technical depth in package layout execution, manufacturability, assembly process constraints, and cross-domain co-design with global silicon design, signal integrity/power integrity, thermal, reliability, and product engineering teams. ### Key Responsibilities Execute package layout design and development for advanced package technologies, including power modules, FCBGA, SiP, WLCSP, and multi-chip modules. Develop and maintain package CAD databases, ensuring accuracy and adherence to package design guidelines, DFM, and DFA requirements to support manufacturability, yield, and long-term reliability. Manage the package design cycle, including schematic creation, netlist import, footprint assignment, layout implementation, verification, and generation of manufacturing release outputs such as Gerber/drill data, fabrication drawings, assembly drawings, bump maps, and related documentation. Create and modify substrate and RDL layouts, bump maps, escape routing, stack-up structures, and power/ground distribution features. Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. Ensure package designs comply with applicable foundry, OSAT, substrate vendor, and manufacturing design rules, including DRC, LVS, connectivity, and netlist verification requirements. Support Engineering Change Order cycles, design updates, revision control, and release documentation throughout the project lifecycle. ## Qualifications 4+ years of hands-on experience in package CAD layout, substrate design, or advanced package development; 6+ years preferred. Strong background in power module packaging, FCBGA, SiP, WLCSP, advanced substrate-based packages, and multi-die/chiplet-based package architectures. High proficiency with industry-standard package design tools such as Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Substrate Integrator, or equivalent CAD platforms. Proven experience applying advanced package design rules, substrate vendor constraints, OSAT assembly requirements, DFM/DFA principles, and manufacturing release standards. Experience interfacing directly with Tier-1 OSATs, substrate suppliers, foundries, silicon design teams, and product engineering teams. Working understanding of SI/PI fundamentals, high-speed routing, impedance control, power/ground distribution, and crosstalk mitigation. Strong communication, presentation, and technical documentation skills, with demonstrated experience working effectively in global, cross-functional engineering environments. ### Education Bachelor's or Master's degree in Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline. ## At a glance - Posted by the employer: Sep 30, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 19 days - Location: Tempe, Arizona, United States - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000152681758-staff-package-design-engineer) ## More jobs at Renesas Electronics ### [Senior Manager, Package Design Engineering](https://jobs.opennash.com/companies/renesas-electronics/jobs/5833401bf4e141f2ca4a/) Tempe, Arizona, United States ### [Senior Staff Package Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/26c8c723118227437bdd/) Tempe, Arizona, United States ### [Senior Product Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/dae5e1b91abf46f2fed0/) Tempe, Arizona, United States ### [Staff Marketing Operations Specialist](https://jobs.opennash.com/companies/renesas-electronics/jobs/479c9bf55d02f1309888/) Tempe, Arizona, United States ### [Test Technician](https://jobs.opennash.com/companies/renesas-electronics/jobs/1fb9e7a0702a045d089c/) Tempe, Arizona, United States ## Similar jobs at other companies ### [Package Design Engineer - Staff](https://jobs.opennash.com/companies/qualcomm/jobs/0f92ad829e5462a761ac/) Qualcomm · San Diego, California, United States of America ### [RF Package Design Engineer, Senior Staff](https://jobs.opennash.com/companies/qualcomm/jobs/07cd9efdf636a5e8f171/) Qualcomm · San Diego, California, United States of America ### [Structural Design Engineer Staff - Level 4](https://jobs.opennash.com/companies/lockheed-martin/jobs/b5bad896118102a464cf/) Lockheed Martin · Marietta, GA ### [Staff Engineer RF Microwave Design](https://jobs.opennash.com/companies/northrop-grumman/jobs/95bcf5c1f35acac8f4ef/) Northrop Grumman · United States-Maryland-Baltimore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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