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Renesas Electronics

# (Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried)

Kaohsiung, Kaohsiung City, Taiwan Full-time Senior individual contributor Design 

Listed on Renesas Electronics’s official careers site. Posted August 31, 2026. Check that it is still open and apply there.
[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000146418229--sr-staff-package-design-engineer-mis-substrate-fc-expose-die-experienced-in-power-or-gan-is-requried-)

[OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / (Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried)

## Job description

### Key Responsibilities
- Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
- Work with OSAT/CM to develop, run DOE to optimize processes, establish process spec & monitor and resolve process issues early in the production to ensure only parts with superior quality shipped to customer.
- Work with Product groups and Reliability team, qualify new packages and processes within required time frame & further address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
- Ensure smooth transition into production & implement ramp up monitor.
- Participate in packaging roadmap development & focus on execution, develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging, flip chip interconnects and panel level package.
- Establish & maintain package design rules.

## Qualifications

### Qualifications and Skills
- Doctorate/Masters / Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
- >10 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging.
- Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software.
- Strong interpersonal and communication skills.
- Strong analytical and presentation skills.
- Knowledge of wire-bonding & multi-chip module technologies is a plus.

## At a glance
- Posted by the employer: Aug 31, 2026
- First seen by OpenNash: Oct 12, 2026
- Last checked: Oct 12, 2026
- Listed for: 42 days
- Location: Kaohsiung, Kaohsiung City, Taiwan
- Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000146418229--sr-staff-package-design-engineer-mis-substrate-fc-expose-die-experienced-in-power-or-gan-is-requried-)

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