[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Renesas Electronics jobs](https://jobs.opennash.com/companies/renesas-electronics/) · [Search jobs](/search/) Renesas Electronics · Plano, TX # Senior Principal Design Verification Engineer Plano, TEXAS, United States Full-time Senior individual contributor Design Listed on Renesas Electronics’s official careers site. Posted September 27, 2026. Check that it is still open and apply there. [Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000152040289-senior-principal-design-verification-engineer-) [OpenNash Jobs](https://jobs.opennash.com/) / [Renesas Electronics](https://jobs.opennash.com/companies/renesas-electronics/) / Senior Principal Design Verification Engineer ## Job description ### Position Overview Renesas is seeking an experienced Principal Verification Engineer to lead the verification efforts for our Automotive PMIC (Power Management Integrated Circuit) product line. This role combines deep expertise in mixed-signal verification methodology with strong leadership capabilities to mentor junior engineers and drive verification strategy across multiple product platforms. The ideal candidate will have comprehensive knowledge of analog, digital, and mixed-signal verification techniques, combined with hands-on experience debugging complex automotive power management systems. ### Key Responsibilities - Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs - Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200) - Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies - Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces - Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners ### Collaborate closely with cross-functional teams - Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs - Mentor and lead junior verification engineers, defining best practices and establishing verification methodologies - Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques - Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions - Create and maintain comprehensive verification documentation, test plans, and coverage ## Qualifications - MS or PhD in Electrical Engineering, Computer Engineering, or related - 12+ years of experience in mixed-signal or analog circuit verification - Deep understanding of all aspects of mixed-signal verification environment architecture and implementation - Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration - Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium) - Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations - Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL - Experience with automotive PMIC or power management IC design and verification - Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages ### Solid understanding of verification methodologies - UVM, assertions, coverage-driven verification ### Experience interfacing with multiple verification domains - functional, post-silicon, ATE test correlation - Excellent problem-solving and debugging skills with strong analytical mindset - Leadership and mentoring experienc ## At a glance - Posted by the employer: Sep 27, 2026 - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 22 days - Location: Plano, TEXAS, United States - Employment type: Full-time[Apply on Renesas Electronics’s careers site →](https://jobs.smartrecruiters.com/RenesasElectronics/744000152040289-senior-principal-design-verification-engineer-) ## More jobs at Renesas Electronics ### [Sr. Staff Project/Program Design](https://jobs.opennash.com/companies/renesas-electronics/jobs/5ca76aa4ccc78ce0534d/) Plano, TEXAS, United States ### [Power System Application Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/75f74163e1ba25b6ec19/) Plano, TEXAS, United States ### [Senior Staff Analog Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/96abd5f7408fbe0bdf94/) Plano, TEXAS, United States ### [Sr Staff Project/Program Manager](https://jobs.opennash.com/companies/renesas-electronics/jobs/cd276d58fbcf3b1a14c2/) Plano, TEXAS, United States ## Similar jobs at other companies ### [Principal Design Verification Engineer - Formal](https://jobs.opennash.com/companies/microsoft/jobs/63c5570160bfdee65271/) Microsoft · United States, North Carolina, Raleigh, Texas, Austin, Oregon, Hillsboro, California, Mountain View ### [Principal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/852fd5d16f618acc3cf7/) Microsoft · United States, California, Mountain View, Washington, Redmond, Texas, Austin, Oregon, Hillsboro, North Carolina, Raleigh ### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/) Qualcomm · Tijuana, Baja California, Mexico ### [Principal Verification Engineer](https://jobs.opennash.com/companies/fortinet/jobs/9f80d3ec584a8024b18d/) Fortinet · Sunnyvale, CA, United States OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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