[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Qualcomm jobs](https://jobs.opennash.com/companies/qualcomm/) · [Search jobs](/search/) Qualcomm · Bangalore, India # Physical Design, Principal Engineer/Director, (Custom Silicon Group) Bangalore, India Director Design Listed on Qualcomm’s official careers site. Posted August 5, 2026. Check that it is still open and apply there. [Apply on Qualcomm’s careers site →](https://careers.qualcomm.com/careers/job/446720216201) [OpenNash Jobs](https://jobs.opennash.com/) / [Qualcomm](https://jobs.opennash.com/companies/qualcomm/) / Physical Design, Principal Engineer/Director, (Custom Silicon Group) ## Job description ### Company Qualcomm India Private Limited ### Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, you will lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout. You will be responsible for driving the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness. In addition to providing technical and organizational leadership, you will serve as a key customer-facing engineering leader, partnering with strategic customers and stakeholders to translate business requirements into successful silicon solutions. You will lead a team of engineers and work closely with cross-functional groups across geographies -- including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics. ### Minimum Qualifications - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ### Principal Duties and responsibilities - Demonstrate proven experience in executing responsibilities across multiple sites. - Lead and manage a team across multiple functions. - Design closure and tapeout expertise in advanced technology nodes. - Complete ownership of PnR implementation, including Floor planning, Placement, CTS, and post-route activities on the cutting-edge nodes. - Possess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV. - Collaborate effectively to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout - Understand deep sub-micron design challenges, including leakage power, signal integrity, and DFM. - Support pre-sales and business development activities by evaluating technical feasibility and providing design expertise. - Provide technical leadership during design reviews and executive-level customer engagements. - Drive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams. ### Minimum Qualifications - Bachelor's or Master’s degree in Electrical/Electronics Engineering and 17- 25 years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs. ### Preferred Qualifications - Excellent hands-on experience on Floor planning, PnR and STA flows - Good knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc. - Thorough understanding of signoff domains– LEC/CLP/PDN etc. - 18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm) ### Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. ### To all Staffing and Recruiting Agencies Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. ## At a glance - Posted by the employer: Aug 5, 2026 - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 20, 2026 - Listed for: 76 days - Location: Bangalore, India[Apply on Qualcomm’s careers site →](https://careers.qualcomm.com/careers/job/446720216201) ## More jobs at Qualcomm ### [ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr](https://jobs.opennash.com/companies/qualcomm/jobs/4ef229954ffd77d7dc88/) Bangalore, India ### [BT - Design Verification Sr Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/8a4545cadb1eb8810d4d/) Bangalore, India ### [BT - Design Verification Staff Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/4d2b145e2239da69b58e/) Bangalore, India ### [CPU Design Sr Staff Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/6f7830736284ef971ce9/) Bangalore, India ## Similar jobs at other companies ### [Physical Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/2d7f9c2e826bc117df12/) Microsoft · India, Karnataka, Bangalore ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [Principal Physical Design Engineer](https://jobs.opennash.com/companies/renesas-electronics/jobs/0c44071fd515792473c6/) Renesas Electronics · Kodaira, Japan ### [Senior Staff Engineer Physical Design and Methodology (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/46bbe226ff31021fb81f/) Infineon Technologies · Munich ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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