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NXP Semiconductors · Multiple locations

# G7 Fellow – High-Speed Interfaces & Clocking Strategy

Multiple locations Operations 

Listed on NXP Semiconductors’s official careers site. Listed as of October 19, 2026. Check that it is still open and apply there.
[Apply on NXP Semiconductors’s careers site →](https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/G7-Fellow---High-Speed-Interfaces---Clocking-Strategy_R-10066820)

[OpenNash Jobs](https://jobs.opennash.com/) / [NXP Semiconductors](https://jobs.opennash.com/companies/nxp-semiconductors/) / G7 Fellow – High-Speed Interfaces & Clocking Strategy

## Job description

### Key Responsibilities

Technology Strategy & Roadmap Leadership Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP. Analyze current and future requirements across all NXP Business Lines and Product Lines. Develop technology roadmaps aligned with market trends, customer needs, and product strategies. Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.

Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position. Portfolio Analysis & Make-or-Buy Decisions Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications. Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities. Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.

Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact. Clocking & PLL Technology Leadership Define company-wide clocking and synchronization strategies. Drive the roadmap for next-generation clock generation and PLL solutions with focus on: Low jitter Low power Small area Scalability across process nodes High-performance operation Functional safety requirements Lead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.

### High-Speed Interface Architecture
- Provide technical leadership for connectivity technologies including: I3C USB / eUSB Ethernet USXGMII MIPI DDR PCIe CXL UCIe Emerging chiplet interconnect technologies
- Guide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.

Innovation & Technical Excellence Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies. Anticipate emerging industry trends and identify opportunities for NXP differentiation. Drive benchmarking, technology assessments, and architectural studies. Foster technical excellence and innovation across engineering communities. Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.

More information about NXP in India... #LI-9415

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 12, 2026
- Last checked: Oct 19, 2026
- Listed for: 7 days
- Location: Multiple locations[Apply on NXP Semiconductors’s careers site →](https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/G7-Fellow---High-Speed-Interfaces---Clocking-Strategy_R-10066820)

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