[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NXP Semiconductors jobs](https://jobs.opennash.com/companies/nxp-semiconductors/) · [Search jobs](/search/) NXP Semiconductors · Pune # Senior Lead Engineer - SoC Design Verification Pune Manager or lead Design Listed on NXP Semiconductors’s official careers site. Listed as of October 19, 2026. Check that it is still open and apply there. [Apply on NXP Semiconductors’s careers site →](https://nxp.wd3.myworkdayjobs.com/careers/job/Pune/Senior-Lead-Engineer---SoC-Design-Verification_R-10064856-1) [OpenNash Jobs](https://jobs.opennash.com/) / [NXP Semiconductors](https://jobs.opennash.com/companies/nxp-semiconductors/) / Senior Lead Engineer - SoC Design Verification ## Job description ### Job Title Senior Design Verification Engineer / Location: Pune Role Overview: We are seeking an experienced Design Verification Engineer with 6+ years of expertise for execution of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low-power design verification, and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills and collaboration in a fast-paced environment. ### Key Responsibilities Develop and own SoC-level and/or IP-level verification suites with coverage goals. Responsible for executing verification plan according to the product specification and verification requirements defined by product architects. Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation. Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality. Familiar with both SoC-level and IP-level verification environments. Collaborate with the team in developing and improving flows for maximum reuse and efficiency. Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off. ### Required Qualifications Experience: 5-12 years in SoC/IP verification with participation in successful tape-outs of SoCs. ### Technical Skills Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV. Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification. Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium). Experience with low-power verification (UPF) is a plus. Gate-level simulations and power-aware simulations is a plus. Good working knowledge of assertions (SVA) and functional coverage. ### Verification of multiple interfaces SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable. Knowledge of Flash memory and security IPs is nice to have. Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage. ### Soft Skills Comfortable working in a fast-paced environment. Strong team player with excellent communication skills. ### Education Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering More information about NXP in India... #LI-2734 ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 7 days - Location: Pune[Apply on NXP Semiconductors’s careers site →](https://nxp.wd3.myworkdayjobs.com/careers/job/Pune/Senior-Lead-Engineer---SoC-Design-Verification_R-10064856-1) ## More jobs at NXP Semiconductors ### [Design Verification Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/09a2a03ee74bfec61a6e/) Pune ### [Lead Design Engineer, SoC Design](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/80590fef0c7437d90383/) Pune ### [Lead Engineer - SoC Design Verification](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/a49922657925154ecd22/) Pune ### [Physical Design Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/8f3dd2fc831b7c8fa75f/) Pune ### [Principal Analog Design Lead - MCU](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/69b9de044fe59c33afaa/) Pune ## Similar jobs at other companies ### [SOC Design Verification Staff Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/6cbdec1f9f8ac9f65878/) Qualcomm · Bangalore, India ### [Principal SOC Performance Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/4978befbe1d83beb7e57/) Microsoft · India, Karnataka, Bangalore ### [Staff ASIC Digital Engineer (SOC Verification, PCIe) with 8 to 12 years of experience](https://jobs.opennash.com/companies/sandisk/jobs/3d2b2a850dec23a8b655/) Sandisk ### [Silicon SoC Design Verification Engineer, HSIO](https://jobs.opennash.com/companies/alphabet/jobs/978b9258032ae4107199/) Alphabet · Bengaluru, Karnataka, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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