[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Multiple locations # Senior Mask Design Engineer - Hardware Multiple locations Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mask-Design-Engineer---Hardware_JR2015599) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Mask Design Engineer - Hardware ## Job description NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to take on, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal circuit designs. ### What you'll be doing Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools. You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Take part in floor planning, custom layout and verifying against design rules and schematics. ### What we need to see Have a BSEE or equivalent experience. Minimum of 7+ years proven experience in Mask and Layout Design. Deep understanding of analog circuit layout concepts in submicron CMOS technologies. You are an authority with Cadence custom circuit design tools - particularly virtuoso. Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield. You are able to work optimally in a team, good interpersonal skills, passion and positive energy. Proficient in scripting languages like perl, python, skill etc. Should have knowledge of DRC and LVS checking flows, ability to customize decks. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until April 6, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 20, 2026 - Listed for: 102 days - Location: Multiple locations[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mask-Design-Engineer---Hardware_JR2015599) ## More jobs at NVIDIA ### [ASIC Design Engineer – Clocks IP](https://jobs.opennash.com/companies/nvidia/jobs/9c7f63d0b4ece0c46f2e/) ### [ASIC Design and STA Engineer](https://jobs.opennash.com/companies/nvidia/jobs/55a504616b4142dab9f9/) ### [ASIC Physical Design Engineer, Netlisting - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/12d0ec2853f1556297c8/) ### [Applied Agentic AI Lead, Partner Co-Design](https://jobs.opennash.com/companies/nvidia/jobs/e14889671d03dda7e34a/) ### [Board Design Engineer, NVLINK](https://jobs.opennash.com/companies/nvidia/jobs/316883757a3d5bae28f7/) ## Similar jobs at other companies ### [ATE Hardware Design - Principal Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/ab4d01db9cee7f1890da/) NXP Semiconductors ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Staff Engineer Layout and Mask Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/ba99a561787308012852/) Infineon Technologies · Bangalore BTP ### [Hardware Design Engineer](https://jobs.opennash.com/companies/ntt/jobs/165fb243218f68a9ef9d/) NTT · Timisoara, Romania ### [Hardware Design Engineer – Application Engineering, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/f5e23b5b2d1c68460bb5/) Qualcomm · Ottawa, Ontario, Canada [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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