[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) NVIDIA · China, Shanghai # ASIC Physical Design Engineer - New College Grad 2027 China, Shanghai Design Listed on NVIDIA’s official careers site. Posted October 27, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Physical-Design-Engineer---New-College-Grad-2027_JR2028452) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / ASIC Physical Design Engineer - New College Grad 2027 ## Job description NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world. ### What you'll be doing Chip integration and netlist generation Synthesis RTL/netlist quality check Formal Verification Constraints creation and validation, timing budget. Work with ASIC team to analyze/resolve special timing issues. Cross-Team collaboration to implement chip partitioning and floorplan - Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level - Achieve special mode timing closure, such as io, test, clock, async etc. Function eco creation Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) Flow automation development for above areas Methodology in any of above areas. ### What we need to see MS in EE or Microelectronics (or equivalent experience) Project experience in IC design implementation Courses taken in circuit design, digital design Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful - Proficient user of Python or TCL is helpful - Proficient in English reading and writing NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! ## At a glance - Posted by the employer: Oct 27, 2026 - First seen by OpenNash: Oct 27, 2026 - Last checked: Nov 3, 2026 - Listed for: 7 days - Location: China, Shanghai[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Physical-Design-Engineer---New-College-Grad-2027_JR2028452) ## Hiring at NVIDIA - Open jobs: 2,719 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Weekly hiring report](/reports/hiring/) ## More jobs at NVIDIA ### [ASIC Design Engineer, Clocks](https://jobs.opennash.com/companies/nvidia/jobs/bba710d2899935021389/) China, Shanghai ### [ASIC Design and Verification Intern, SOC - 2027](https://jobs.opennash.com/companies/nvidia/jobs/dfe0815c668f1489c96d/) China, Shanghai ### [ASIC Engineer, Networking Chip Design - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/85e5c0da92e8a7e86a4a/) China, Shanghai ### [ASIC Engineering Intern, Networking Chip Design - 2027](https://jobs.opennash.com/companies/nvidia/jobs/3aa5cff2c3757b77e047/) China, Shanghai ### [ASIC Physical Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/e9748c0389d184886001/) China, Shanghai ## Similar jobs at other companies ### [ASIC Engineer - Block Level Physical Design Engineer - Armenia - ETR](https://jobs.opennash.com/companies/cisco-systems/jobs/1d172182ef24e9a32db8/) Cisco Systems · Armenia ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [ASIC/FPGA Design Verification Engineer, Senior](https://jobs.opennash.com/companies/qualcomm/jobs/f7cc8fb7b0460376d7d6/) Qualcomm · Ottawa, Ontario, Canada ### [Senior ASIC Digital Engineer (SOC Design) 5-8 years](https://jobs.opennash.com/companies/sandisk/jobs/8993cb1565f03b6b02be/) Sandisk ### [Senior ASIC RTL Design Engineer](https://jobs.opennash.com/companies/arrow-electronics/jobs/cf8672ee2af299b7f097/) Arrow Electronics · Remote, Noida-, Uttar Pradesh, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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