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NVIDIA · China, Shanghai

# ASIC Design Engineer, Clocks

China, Shanghai Design 

Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there.
[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Design-Engineer--Clocks_JR2020494)

[OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / ASIC Design Engineer, Clocks

## Job description

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the clocking requirements for the chip, and work with backend teams to understand the physical restrictions. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

### What you’ll be doing

As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints. You will need to run and enhance some in-house flow to guarantee the good quality of clocks RTL and netlist, drive the issues to close. Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams.

You will use Perl/Python to improve the productivity of the above teams. Collaborate with software and silicon solution team to debug GPU clock silicon bugs in our new products.

### What we need to see

BS or (MS preferred) in EE or equivalent experience. 2+ years of meaningful work experience. Your ability to thrive in a dynamically changing environment. Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages. Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.

Good understanding of backend flows and requirements is a plus. DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable. Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills. Good team work spirit, easy to cooperate with team members.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Aug 20, 2026
- Last checked: Oct 20, 2026
- Listed for: 61 days
- Location: China, Shanghai[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Design-Engineer--Clocks_JR2020494)

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