[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior Photonic Layout Design Engineer US, CA, Santa Clara Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Photonic-Layout-Design-Engineer_JR2017453) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Photonic Layout Design Engineer ## Job description Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join our diverse team today! ### What You'll Be Doing As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness. You will work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers to drive next-generation Silicon Photonics (SiPh) and SERDES products. ### Layout Execution & Tape-out Ownership Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation. ### Verification & Mitigation Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out. ### Test Vehicle & Component Development Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows. ### Automation & AI-Assisted Workflows Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows. ### What We Need to See To succeed in this role, candidates must possess a deep technical understanding of advanced node semiconductor fabrication, sophisticated automation capabilities, and a proven track record of first-time success on high-density chip designs. BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience). At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries. Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies. Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield). Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows. Ability to optimize workflows using best-known methods (BKMs), and proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until May 22, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 20, 2026 - Listed for: 102 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Photonic-Layout-Design-Engineer_JR2017453) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [PCB Layout Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/223f969626c59a23169e/) Lockheed Martin · Orlando, FL ### [Microwave Design and Layout Engineer](https://jobs.opennash.com/companies/microsoft/jobs/df35e663dde63739f396/) Microsoft · United States, Washington, Redmond ### [CPU SRAM Design & Layout Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/ca3c118d3af3d7fb2dba/) Qualcomm · Santa Clara, California, United States of America ### [Staff Photonic Integrated Circuit Design Engineer](https://jobs.opennash.com/companies/nokia/jobs/66d238955ec746617ff1/) Nokia · United States ### [Senior SerDes & Analog Layout Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/2e4faa4fba390e5703a2/) Microsoft · United States, North Carolina, Raleigh, Texas, Austin, District of Columbia, Washington D.C., Washington, Redmond, Idaho, Boise, Oregon, Hillsboro, California, Mountain View OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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