[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Us, CA # Package Layout Engineer - Hardware US, CA, Santa Clara +5 more Remote Full-time Operations Listed on NVIDIA’s official careers site. Posted October 13, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Package-Layout-Engineer---Hardware_JR2027542-1) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Package Layout Engineer - Hardware ## Job description NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. ### What you'll be doing As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages. Optimize package pinout incorporating system level trade-offs of pins assignment. Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. Develop symbols and CAD library databases using Cadence APD design tools Develop methodologies to improve layout productivity What we need to see: Hold a B.S. Electrical Engineering or equivalent experience 2+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. ### Experience with HDI designs is a plus - Proven experience in substrate layout of wire bond and flip chip packages, preferred Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager) - Solid understanding of high-speed design signal integrity practices Experience with Virtuoso and Calibre is a plus Experience using Valor is helpful NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 108,000 USD - 184,000 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 17, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 13, 2026 - First seen by OpenNash: Oct 20, 2026 - Last checked: Oct 20, 2026 - Listed for: 7 days - Location: US, CA, Santa Clara +5 more - Work arrangement: Remote - Employment type: Full-time[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Package-Layout-Engineer---Hardware_JR2027542-1) ## More jobs at NVIDIA ### [Mask Design Engineer – Hardware](https://jobs.opennash.com/companies/nvidia/jobs/08ef522e875da0a6f8b2/) US, CA, Santa Clara +5 more ### [AI Agent Development Engineer (RDSS Intern)](https://jobs.opennash.com/companies/nvidia/jobs/2f91bc3eab392a3e69e8/) ### [AI Compute Engineer - NVIS](https://jobs.opennash.com/companies/nvidia/jobs/7597aa98e58b0743ef8a/) ### [AI Computing Development Engineer, TensorRT and TensorRT-LLM AIGV](https://jobs.opennash.com/companies/nvidia/jobs/1217f25a5a18c044a936/) ### [ASIC CAD Engineer, Clocks Methodology](https://jobs.opennash.com/companies/nvidia/jobs/7e0f948ddd5a0695fb53/) India, Bengaluru ## Similar jobs at other companies ### [Hardware Engineer, PCB Layout](https://jobs.opennash.com/companies/meta-platforms/jobs/1dace888842c4cc00d7d/) Meta Platforms · Menlo Park, CA ### [Staff Engineer, Hardware Design (PCB Layout)](https://jobs.opennash.com/companies/celestica/jobs/249201ab167b5ea0fe41/) Celestica · Austin, TX, US ### [Package Layout Design Engineer, Annapurna Labs - AI Silicon Packaging](https://jobs.opennash.com/companies/amazon/jobs/e1b91186671919c7b539/) Amazon · US, AZ, Tempe ### [Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging](https://jobs.opennash.com/companies/amazon/jobs/74cac8f83a0217b520d4/) Amazon · US, AZ, Tempe ### [PCB Layout Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/223f969626c59a23169e/) Lockheed Martin · Orlando, FL OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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