[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Signal Integrity and PCB Design Engineer US, CA, Santa Clara Design Listed on NVIDIA’s official careers site. Posted October 7, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Signal-Integrity-and-PCB-Design-Engineer_JR2026807) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Signal Integrity and PCB Design Engineer ## Job description We are looking for a Signal Integrity & PCB design Engineer! NVIDIA is powering the next wave of AI and accelerated computing, and our PCB technology is a critical enabler of the world's highest-performance systems. Join our SI team to ensure that every board we ship meets the most demanding signal integrity requirements — from early material research through high-volume manufacturing. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. If you love solving complex signal integrity challenges and thrive on bridging the gap between design intent and manufacturing reality, we want to hear from you. ### What you'll be doing Lead SI design activities, PCB stackup design, material selection, design guide implementation and post-layout analysis System-level signal integrity simulation of PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB and other interfaces. Analyze and optimize Power delivery network (PDN) on PCBs. Work closely with Package and PCB Design teams crafting solutions for system SI/PI performance TDR & VNA measurement for PKG/PCB material characterization and model correlation What we need to see: BS/MS in Electrical Engineering (or equivalent experience) with minimum 2+ years of experience as a SI/PI engineer Deep understanding of electromagnetics, transmission line theory and various channel components. Experienced with Cadence Allegro PCB designer and Constraints Manager and or other PCB stackup designer tools Understanding of impacts of high-volume PCB manufacturing on channel signal integrity Experience with SI channel design solutions for industry standard interface like PCIE, DRAM, MIPI, HDMI, USB etc. Hands on experience with HFSS, Sigrity, Hspice and/or similar industry standard tools Ways to stand out from the crowd: Experience of SI/PI design sign off process at platform level - Familiarity with PCB fabrication process, understanding of PCB and package material choice impact on SI performance - Familiarity with high-speed transmitter, receiver design, and various equalization schemes Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 10, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 7, 2026 - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 20, 2026 - Listed for: 13 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Signal-Integrity-and-PCB-Design-Engineer_JR2026807) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [Signal Integrity (SI) and Power Integrity (PI) Senior Principal Engineer II](https://jobs.opennash.com/companies/bae-systems/jobs/af227f891621d75ca828/) BAE Systems · Nashua, New Hampshire, United States ### [PCB Design Engineer – System Lead, Signal Integrity, and System Architecture (Onsite)](https://jobs.opennash.com/companies/cisco-systems/jobs/020c026fad505b259ec6/) Cisco Systems · Milpitas, California, United States of America ### [Principal Signal Integrity Simulation Engineer](https://jobs.opennash.com/companies/microsoft/jobs/65673a7b4d2d648f7b4a/) Microsoft · United States, Washington, Redmond ### [Sr. Signal Integrity Lab Engineer](https://jobs.opennash.com/companies/microsoft/jobs/8da1f341e90cc22906d3/) Microsoft · United States, Washington, Redmond ### [Signal Integrity Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/3aedec09e717bd65b77b/) Qualcomm · San Diego, California, United States of America [Jobs in Santa Clara, CA](/locations/us/ca/santa-clara/)[Jobs in California](/locations/us-ca/)[Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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