[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) NVIDIA · China, Shanghai # Power Methodology and Analysis Engineer China, Shanghai Operations Listed on NVIDIA’s official careers site. Posted October 30, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/Power-Methodology-and-Analysis-Engineer_JR2028881) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Power Methodology and Analysis Engineer ## Job description We are now looking for a Power Methodology and Analysis Engineer. NVIDIA prides ourselves in having energy efficient products. We believe that continuing to maintain our products' energy efficiency compared to competition is key to our continued success. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and responsible for analyzing fullchip and unit-level power data, and driving ASIC teams to improve their units’ power efficiency. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of NVIDIA chips. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Tegra SOCs. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. ### What you'll be doing Continuously improve the performance and efficiency of power analysis tools. - Develop advanced power optimization tools to empower both front ‑ end and back ‑ end design teams to improve power efficiency - Use internally developed tools and industry standard pre ‑ silicon gate ‑ level and RTL power analysis tools, to help improve product power efficiency - Develop and share best practices for performing pre-silicon power analysis, Enhance internal power tools and automate best practices - Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny. Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes. ### What we need to see MS with 1-3 years of experience (or PhD preferred) in related fields. Basic understanding of concepts of energy consumption, estimation, and low power design. Familiarity with Verilog and ASIC design principles, including knowledge of logic cells. Good verbal/written English and interpersonal skills; much collaboration with design teams is expected. Strong coding skills, preferably in Python, C++. Ability to formulate and analyze algorithms, and comment on their time complexity and memory consumption. Desire to bring data-driven decision-making and analytics to improve our products. ### Ways to stand out from the crowd Familiarity with power tools and flow development is a big plus Hands ‑ on experience leveraging AI tools for engineering productivity is a big plus. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. ## At a glance - Posted by the employer: Oct 30, 2026 - First seen by OpenNash: Nov 3, 2026 - Last checked: Nov 10, 2026 - Listed for: 11 days - Location: China, Shanghai[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/Power-Methodology-and-Analysis-Engineer_JR2028881) ## Hiring at NVIDIA - Open jobs: 2,784 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Weekly hiring report](/reports/hiring/) ## More jobs at NVIDIA ### [Senior AI Agent Test Development Engineer, SDET](https://jobs.opennash.com/companies/nvidia/jobs/2832afd5341438bbd2b1/) China, Shanghai ### [Senior AI Infra Test Development Engineer, SDET](https://jobs.opennash.com/companies/nvidia/jobs/9f61f0cadfb978f11a1f/) China, Shanghai ### [Senior AI Video Architecture Engineer](https://jobs.opennash.com/companies/nvidia/jobs/ec752668b4cb9f7e12ab/) China, Shanghai ### [Senior ASIC Engineer](https://jobs.opennash.com/companies/nvidia/jobs/fdd4b19cdda3802d4a00/) China, Shanghai ### [Senior ASIC Verification Engineer - PMU](https://jobs.opennash.com/companies/nvidia/jobs/32754fabb200fc655ee8/) China, Shanghai ## Similar jobs at other companies ### [Senior Engineer - Diagnostics Systems & Methodology](https://jobs.opennash.com/companies/qualcomm/jobs/2ab2b898ac3b597ac1d2/) Qualcomm · Bangalore, India ### [Staff Engineer – STA Methodology/CAD](https://jobs.opennash.com/companies/qualcomm/jobs/2dc290681e6a81eb1833/) Qualcomm · Bangalore, India ### [Senior Staff Engineer Reliability Methodology](https://jobs.opennash.com/companies/infineon-technologies/jobs/2a6c611043faa4c1b26f/) Infineon Technologies · Melaka ### [Principal Physical Design Engineer - SoC Floorplanning & Methodology](https://jobs.opennash.com/companies/microsoft/jobs/5edaf1b19a06b06a7a99/) Microsoft · United Kingdom, London ### [Internal Audit Methodology & Quality Assurance Manager](https://jobs.opennash.com/companies/abb/jobs/5ce13b6fef9737bbce0c/) ABB · Rotterdam, South Holland, Netherlands [Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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