[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/)

NVIDIA · Multiple locations

# Senior Mask Layout Design Engineer

Multiple locations Senior individual contributor Design 

Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there.
[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Mask-Layout-Design-Engineer_JR2024209)

[OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Mask Layout Design Engineer

## Job description

We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

### What you'll be doing

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include floor planning, custom layout and verifying against design rules and schematics.

### What we need to see

BSEE or equivalent experience Minimum of 5+ years of relevant mask design / layout experience Deep understanding of analog circuit layout concepts in submicron CMOS technologies; You are an expert with Cadence custom circuit design tools - particularly virtuoso. Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield You are able to communicate in spoken and written English.

Work effectively in a team, good communication skills, enthusiasm and positive energy. Proficiency in scripting languages like perl, python, skill, etc.; Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 13, 2026
- Last checked: Oct 20, 2026
- Listed for: 7 days
- Location: Multiple locations[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Mask-Layout-Design-Engineer_JR2024209)

## More jobs at NVIDIA

### [ASIC Design Engineer – Clocks IP](https://jobs.opennash.com/companies/nvidia/jobs/9c7f63d0b4ece0c46f2e/)

### [ASIC Design and STA Engineer](https://jobs.opennash.com/companies/nvidia/jobs/55a504616b4142dab9f9/)

### [ASIC Physical Design Engineer, Netlisting - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/12d0ec2853f1556297c8/)

### [Applied Agentic AI Lead, Partner Co-Design](https://jobs.opennash.com/companies/nvidia/jobs/e14889671d03dda7e34a/)

### [Board Design Engineer, NVLINK](https://jobs.opennash.com/companies/nvidia/jobs/316883757a3d5bae28f7/)

## Similar jobs at other companies

### [CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)](https://jobs.opennash.com/companies/intel/jobs/30c80f7a8b13ac3f9045/)

Intel 

### [E-Core (Atom) CPU Layout Design Engineer](https://jobs.opennash.com/companies/intel/jobs/e54941c848d40dbb180f/)

Intel 

### [Senior Engineer, OCT CPEE Central Mask Tape out](https://jobs.opennash.com/companies/micron-technology/jobs/69bc9b0c8a067aa37f21/)

Micron Technology 

### [Staff Engineer Layout and Mask Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/ba99a561787308012852/)

Infineon Technologies · Bangalore BTP

### [Mask Layout Designer](https://jobs.opennash.com/companies/qualcomm/jobs/3987d64fb94359855e5c/)

Qualcomm · Markham, Ontario, Canada

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)