[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior Digital Design Engineer - High-Speed I/O and Photonics US, CA, Santa Clara Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Digital-Design-Engineer---High-Speed-I-O-and-Photonics_JR2018150) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Digital Design Engineer - High-Speed I/O and Photonics ## Job description NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. The mixed-signal high-speed I/O group delivers innovative PHY designs that power the most powerful AI systems in the world today. Our portfolio includes PHY IPs and Chips for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand. We recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. We enable groundbreaking technology that continually pushes the limits of wireline communication! ### What You'll Be Doing While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips. You will participate in chip-level features, programming model and application interface definitions. You will collaborate closely with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and P&R feedbacks is a critical step toward the most optimized product. For post-silicon, you will actively participate in silicon bring-up, build testing scripts for debugging, characterization, performance tuning, and production. You will also work with cross-functional teams to ensure successful production. ### What We Need to See B.S. or M.S. degree in Electrical Engineering or equivalent experience. 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures. Good understanding of design for test, timing constraints, and static timing analysis. Experience with industry verification methodologies, such as UVM. ### Ways to stand out from the crowd Knowledge of optical transceiver devices and integrated components such as modulators, detectors, and TIAs. Experience with SerDes architecture and building blocks such as CDR, DFE, CTLE, TXFIR. Experience with digital assist analog designs, such as calibrations. Familiarity with mixed-signal circuit design concepts and experience in behavior modeling of mixed-signal circuits. Knowledge of physical layer and communication protocols, such as Ethernet, InfiniBand, PCIe, and USB. Understanding of on-chip microcontrollers and standard peripherals, with exposure to hardware and firmware co-design. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until June 12, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 20, 2026 - Listed for: 102 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Digital-Design-Engineer---High-Speed-I-O-and-Photonics_JR2018150) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/86bfab27b3fb25f16774/) Qualcomm · San Diego, California, United States of America ### [Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/fc7941a2f0e160116c2c/) Qualcomm · San Diego, California, United States of America ### [Hardware Engineer Stf/ Digital Design](https://jobs.opennash.com/companies/lockheed-martin/jobs/f4e1a8002ca8a210de04/) Lockheed Martin · Owego, NY ### [Senior Digital Design Engineer](https://jobs.opennash.com/companies/general-dynamics/jobs/0a68d564e4cc2006abf5/) General Dynamics · Scottsdale, AZ, US ### [Electronics Engineer III, Digital Circuit Design](https://jobs.opennash.com/companies/lockheed-martin/jobs/582ca79960fb716eedca/) Lockheed Martin · Littleton, CO OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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