[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Multiple locations # Senior Logic Design Engineer, Cache Coherent Interconnects Multiple locations Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Logic-Design-Engineer--Cache-Coherent-Interconnects_JR2014881) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Logic Design Engineer, Cache Coherent Interconnects ## Job description We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. ### What you'll be doing As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation. Collaborate with our verification team to verify the correctness of your unit. Work with implementation to achieve your timing, area, performance and power goals. Assist with timing closure of super units. ### What we need to see Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience. 5+ years of experience in processor or other related high performance semiconductor designs. Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus. A strong background in computer architecture, cache coherency or high speed interconnects is helpful NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous and love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until March 22, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 20, 2026 - Listed for: 7 days - Location: Multiple locations[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Logic-Design-Engineer--Cache-Coherent-Interconnects_JR2014881) ## More jobs at NVIDIA ### [ASIC Design Engineer – Clocks IP](https://jobs.opennash.com/companies/nvidia/jobs/9c7f63d0b4ece0c46f2e/) ### [ASIC Design and STA Engineer](https://jobs.opennash.com/companies/nvidia/jobs/55a504616b4142dab9f9/) ### [ASIC Physical Design Engineer, Netlisting - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/12d0ec2853f1556297c8/) ### [Applied Agentic AI Lead, Partner Co-Design](https://jobs.opennash.com/companies/nvidia/jobs/e14889671d03dda7e34a/) ### [Board Design Engineer, NVLINK](https://jobs.opennash.com/companies/nvidia/jobs/316883757a3d5bae28f7/) ## Similar jobs at other companies ### [GPU Logic Design Engineer](https://jobs.opennash.com/companies/intel/jobs/55f8484da6d9bca7aea1/) Intel ### [Technical Staff Engineer-Design (Digital Logic)](https://jobs.opennash.com/companies/microchip-technology/jobs/dd85f6c46f0f47b6ad62/) Microchip Technology ### [Sr. Principal Foundry Engineer – Logic/RF Device Expert](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/1c6006388dc7a2242041/) NXP Semiconductors ### [Senior Logic Design Engineer - Microsoft Azure](https://jobs.opennash.com/companies/microsoft/jobs/218c1b875656e03bca74/) Microsoft · Israel, Haifa, Multiple Locations ### [Senior Staff Engineer - Linux Kernel Development (System Cache/MPAM)](https://jobs.opennash.com/companies/qualcomm/jobs/00de81ae2c5f64cb0225/) Qualcomm · Bangalore, India [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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