[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior Mixed Signal Design Engineer US, CA, Santa Clara Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2019412) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior Mixed Signal Design Engineer ## Job description Are you ready to take innovation further? At NVIDIA, we don’t just follow the industry; we define the next generation of connectivity. We seek a visionary Analog/Mixed-Signal Engineer to build and implement high-speed Serdes reaching 80Gbps and beyond. If you enjoy working with deep-submicron CMOS and excel in FinFET technology’s complexities and want to see your work evolve from a blank schematic to high-performance silicon, this is your opportunity. Join us and be part of a company transforming computer graphics, PC gaming, and accelerated computing! ### What you'll be doing Architect the Future: Take full ownership of high-speed Serdes architectures and transistor-level builds, pushing data rates to 80Gbps and higher. ### Silicon Ownership Drive the entire lifecycle—from initial concept and schematic entry to layout, verification, and final silicon characterization. ### Master the Physics Optimize complex circuits for peak system performance, balancing noise, power, and loop stability in deep-submicron nodes. ### Collaborative Precision Partner closely with layout engineers to provide strategic floorplanning and high-speed routing mentorship that ensures design integrity. ### Solve the Impossible Lead post-silicon bring-up and debugging efforts, translating real-world data into build refinements. ### What we need to see MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience in the industry. Minimum 5 plus years of professional Analog Build experience, with a deep portfolio in FinFET and deep-submicron CMOS processes. ### The Toolkit Proficiency in the Cadence Virtuoso environment and a "black belt" in simulation tools (Spectre, HSpice, FineSim, or XA). ### Analytical Rigor Expertise in noise analysis, Monte Carlo simulations, and complex loop stability. Rich experience in high-speed data and/or clock path design. ### Modeling Mastery Proven ability in the modeling, timing, and functionality of both analog and digital circuits to streamline top-level verification. ### The X-Factor You go beyond working in a silo. You are a collaborative teammate who communicates clearly and solves problems with a "find a way" mentality. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 6, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 20, 2026 - Listed for: 102 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2019412) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [Senior Staff Engineer, Analog Mixed Signal Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/5bcb6b66b7e1a74b1acf/) Infineon Technologies · Irvine, CA ### [Analog/Mixed Signal ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/798ef1101649c25b5f1d/) Qualcomm · San Diego, California, United States of America ### [Mixed Signal RTL Design Engineer](https://jobs.opennash.com/companies/apple/jobs/daec80e3e4af3d4dd7bc/) Apple · Cupertino, United States of America [Jobs in Santa Clara, CA](/locations/us/ca/santa-clara/)[Jobs in California](/locations/us-ca/)[Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)