[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Silicon Validation Engineer US, CA, Santa Clara Full-time Operations Listed on NVIDIA’s official careers site. Posted October 13, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Silicon-Validation-Engineer_JR2022641) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Silicon Validation Engineer ## Job description NVIDIA Silicon Co-design Group is seeking a versatile engineer to join the HW ArchDev Methodology team. SCG operates across the full product lifecycle—from early architecture definition through silicon bring-up to production—providing a unique end-to-end perspective on next-generation systems You define how validation is done. Not how it's been done, how it should be done, for chips that don't exist yet. NVIDIA's HW ArchDev Methodology team sits at a rare intersection: architecture, silicon bring-up, and production, all in one group. We build the validation strategies, automation frameworks, and telemetry systems that determine whether next-generation GPUs and AI accelerators ship on time and at quality. The problems are novel. The stakes are real. ### What you’ll be doing - Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency Profile real workloads: training, inference, HPC, video, and emerging applications - Deploy automation and telemetry pipelines that scale across products and teams - Drive silicon bring-up and root-cause debug with reusable, high-leverage methods What we need to see: BS/MS in EE/CE (or equivalent experience) - 4+ years in silicon bring-up, ASIC validation, or system-level debug Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip) Understanding of firmware/driver-hardware interaction Experience or curiosity around data-driven workflows, telemetry, and AI/LLM-assisted development Thrive in a collaborative environment. ### Ways to Stand Out from the crowd You've applied AI/ML or LLMs to validation, debug automation, or workload analysis, not just mentioned it You've built infrastructure others still use: pipelines, observability systems, debug tools You have artifacts: postmortems, test methods, tools, papers, or dashboards that show how you think You've driven cross-functional work across architecture, firmware, validation, and manufacturing If you've ever looked at a validation process and redesigned it from first principles, we want to talk! #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 17, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 13, 2026 - First seen by OpenNash: Oct 20, 2026 - Last checked: Oct 20, 2026 - Listed for: 7 days - Location: US, CA, Santa Clara - Employment type: Full-time[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Silicon-Validation-Engineer_JR2022641) ## More jobs at NVIDIA ### [ASIC Clocks Verification Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/634d881f29a7a2632449/) US, CA, Santa Clara ### [ASIC Verification Engineer](https://jobs.opennash.com/companies/nvidia/jobs/52c13f6335fb98e58de1/) US, CA, Santa Clara ### [ASIC Verification Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/9d98fd56c400ae295ad5/) US, CA, Santa Clara ### [ATE Test Development Engineer](https://jobs.opennash.com/companies/nvidia/jobs/bca8e15f7545d3c56e87/) US, CA, Santa Clara ## Similar jobs at other companies ### [Post-Silicon Validation - Senior Engineer](https://jobs.opennash.com/companies/infineon-technologies/jobs/47881477a7587076ecf3/) Infineon Technologies · San Jose, CA ### [Graphics System/Silicon Validation Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/c2c49f0160a84ff26ade/) Qualcomm · San Diego, California, United States of America ### [Microprocessor Silicon Validation and Optimization Engineer-Staff](https://jobs.opennash.com/companies/qualcomm/jobs/f3dc3fe888eb12a0c09e/) Qualcomm · Austin, Texas, United States of America ### [Silicon Validation Engineer, Infra Silicon](https://jobs.opennash.com/companies/meta-platforms/jobs/427c94e69d1469a6f3c0/) Meta Platforms · Sunnyvale, CA [Jobs in Santa Clara, CA](/locations/us/ca/santa-clara/)[Jobs in California](/locations/us-ca/)[Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)