[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior ASIC Design Engineer - Memory Subsystem US, CA, Santa Clara Full-time Senior individual contributor Design Listed on NVIDIA’s official careers site. Posted October 13, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Memory-Subsystem_JR2027771) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior ASIC Design Engineer - Memory Subsystem ## Job description Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team! ### What you'll be doing As a member of our Memory Subsystem Design team, you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers and memory accelerators are among the industry's most sophisticated because of the complex area, latency, power, bandwidth and quality-of-service requirements. In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies. ### What we need to see BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience) - 5+ years of experience Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches is a plus Experience with multiple clock domains and asynchronous interfaces is a plus - Knowledge of industry specifications like CHI/CXL/PCI-E is a plus. Strong proficiency of Verilog or VHDL. Scripting language like PERL NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 17, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 13, 2026 - First seen by OpenNash: Oct 20, 2026 - Last checked: Oct 20, 2026 - Listed for: 7 days - Location: US, CA, Santa Clara - Employment type: Full-time[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Memory-Subsystem_JR2027771) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/86bfab27b3fb25f16774/) Qualcomm · San Diego, California, United States of America ### [Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/fc7941a2f0e160116c2c/) Qualcomm · San Diego, California, United States of America ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/) Lockheed Martin · Boulder, CO ### [Memory Hardware Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/a085758c5fdaa546bc30/) Microsoft · United States, Idaho, Boise, Washington, Redmond OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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