[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior ASIC Design Engineer - DFT US, CA, Santa Clara Senior individual contributor Design Listed on NVIDIA’s official careers site. Posted October 7, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior ASIC Design Engineer - DFT ## Job description We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. ### What You’ll Be Doing As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams. Your key responsibilities would include: Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs. Develop, deploy, and enhance DFT methodologies for scalability and future product needs. Define and align feature sets by working closely with architects, platform, and software teams. Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration. Create and execute test plans to support both functional and DFT full-chip verification. Support post-silicon bring-up and validation efforts including debug and issue resolution. Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance. ### What we need to see Bachelors degree (or equivalent experience) with 8+ years of experience, or Master’s degree in Electrical Engineering or related field with 6+ years experience. 5+ years of hands-on experience in SoC architecture, RTL design, and verification. Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus.) Deep expertise in DFT design, methodology, and implementation. Familiarity with related domains such as clocking, STA, place & route, and power optimization. Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis. Proficiency in scripting languages such as Python, Perl, or Tcl. Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges. Why Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 14, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 7, 2026 - First seen by OpenNash: Jul 17, 2026 - Last checked: Oct 20, 2026 - Listed for: 95 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883) ## More jobs at NVIDIA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/nvidia/jobs/43f31ed2cc68359a6eb3/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/1f49ca2bc1e479a84171/) US, CA, Santa Clara ### [ASIC Design Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/fc9c26d2c4e94a2e074b/) US, CA, Santa Clara ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) US, CA, Santa Clara ## Similar jobs at other companies ### [ASIC Design-for-Test (DFT) Engineer Intern](https://jobs.opennash.com/companies/keysight-technologies/jobs/9108388acb69aab0821f/) Keysight Technologies · Colorado Springs, Colorado ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/) Lockheed Martin · Boulder, CO ### [ASIC Design Verification Engineer, DFT](https://jobs.opennash.com/companies/meta-platforms/jobs/fee47c6ceec8a41b9c8a/) Meta Platforms · Sunnyvale, CA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/99c4aabaf2f51a99dc1b/) Qualcomm · San Diego, California, United States of America [Jobs in Santa Clara, CA](/locations/us/ca/santa-clara/)[Jobs in California](/locations/us-ca/)[Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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