[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Multiple locations # Senior PCIe Design Verification Engineer Multiple locations Senior individual contributor Design Listed on NVIDIA’s official careers site. Listed as of October 20, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/Taiwan-Taipei/Senior-PCIe-Design-Verification-Engineer_JR2019927) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior PCIe Design Verification Engineer ## Job description NVIDIA is seeking elite Senior Verification Engineers to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs by developing scalable testbench that is re-usable across different verification methodologies and environments. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” ### What you’ll be doing Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e. Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments. Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology. Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Collaborate with multiple verification teams, architects, designers, and pre and post silicon verification teams to accomplish your tasks. ### What we need to see Bachelors or Masters degree with 5+ years of experience in Unit/Sub-system/SOC level verification Proficiency in SystemVerilog Expertise in comprehensive verification of industry standard IP or interconnect protocols (e.g. PCI Express, CXL, UCIe, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Skillful in verification methodologies like UVM, Specman/e, as well as re-usable testbench architecture and its development Exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Familiarity with both UVM and Specman/e based verification methodologies Good knowledge of PCIE protocol - Gen3 and above Great debugging and analytical skills Excellent interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 20, 2026 - Listed for: 102 days - Location: Multiple locations[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/Taiwan-Taipei/Senior-PCIe-Design-Verification-Engineer_JR2019927) ## More jobs at NVIDIA ### [ASIC Design Engineer – Clocks IP](https://jobs.opennash.com/companies/nvidia/jobs/9c7f63d0b4ece0c46f2e/) ### [ASIC Design and STA Engineer](https://jobs.opennash.com/companies/nvidia/jobs/55a504616b4142dab9f9/) ### [ASIC Physical Design Engineer, Netlisting - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/12d0ec2853f1556297c8/) ### [Applied Agentic AI Lead, Partner Co-Design](https://jobs.opennash.com/companies/nvidia/jobs/e14889671d03dda7e34a/) ### [Board Design Engineer, NVLINK](https://jobs.opennash.com/companies/nvidia/jobs/316883757a3d5bae28f7/) ## Similar jobs at other companies ### [GPU Design Verification Engineer](https://jobs.opennash.com/companies/intel/jobs/89dbb37da1844fe2847d/) Intel ### [Mixed Signal Design Verification Engineer](https://jobs.opennash.com/companies/intel/jobs/af8004ba66baa3586799/) Intel ### [ASIC Design and Verification Engineer - AI](https://jobs.opennash.com/companies/analog-devices/jobs/deca9bfbf25b66b055eb/) Analog Devices ### [Staff ASIC Digital Engineer (SOC Verification, PCIe) with 8 to 12 years of experience](https://jobs.opennash.com/companies/sandisk/jobs/3d2b2a850dec23a8b655/) Sandisk ### [Experienced system Design Engineer- PCIE Expert](https://jobs.opennash.com/companies/sandisk/jobs/d6e60534d9f8645baf0b/) Sandisk [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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