[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Santa Clara, CA # Senior DFT Power Methodology Engineer US, CA, Santa Clara Senior individual contributor Operations Listed on NVIDIA’s official careers site. Posted October 17, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Power-Methodology-Engineer_JR2021098-1) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / Senior DFT Power Methodology Engineer ## Job description NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. ### What you'll be doing As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. Help mentor junior engineers on test designs and trade-offs including cost and quality. ### What we need to see BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus. Experience in application of AI for EDA-related problem-solving is a plus. Excellent knowledge in using statistical tools for data analysis & insights. Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power. Experience in Silicon debug and bring-up on the ATE or SLT platforms. Be able to think like a programmer so that this can be translated into action using AI Coding harnesses Ways to stand out from the crowd: Outstanding written and oral communication skills with the curiosity to work on rare challenges. Experience in managing DFT Power Methodology for designs Experience in post-silicon debug for thermal & IR Drop Good understanding of technology and passionate about what you do Strong collaborative and interpersonal skills, specifically a proven ability to effectively guide and influence within a dynamic environment NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most forward-thinking and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 17, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Oct 17, 2026 - First seen by OpenNash: Jul 17, 2026 - Last checked: Oct 20, 2026 - Listed for: 95 days - Location: US, CA, Santa Clara[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Power-Methodology-Engineer_JR2021098-1) ## More jobs at NVIDIA ### [ASIC Clocks Verification Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/634d881f29a7a2632449/) US, CA, Santa Clara ### [ASIC Verification Engineer](https://jobs.opennash.com/companies/nvidia/jobs/52c13f6335fb98e58de1/) US, CA, Santa Clara ### [ASIC Verification Engineer - New College Grad 2027](https://jobs.opennash.com/companies/nvidia/jobs/9d98fd56c400ae295ad5/) US, CA, Santa Clara ### [ATE Test Development Engineer](https://jobs.opennash.com/companies/nvidia/jobs/bca8e15f7545d3c56e87/) US, CA, Santa Clara ## Similar jobs at other companies ### [ASIC Timing and Methodology Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/9a3a66e840e1ae3025fb/) Qualcomm · Tijuana, Baja California, Mexico ### [Emulation Performance Methodology & Debug Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/571d0163a463c21368ea/) Qualcomm · Tijuana, Baja California, Mexico ### [Senior Engineer Digital Verification and Methodology](https://jobs.opennash.com/companies/infineon-technologies/jobs/2d16b46260c7b36e8f08/) Infineon Technologies · Lexington, KY ### [Staff Engineer Digital Verification and Methodology](https://jobs.opennash.com/companies/infineon-technologies/jobs/d9074188ee6fe932ddd6/) Infineon Technologies · Lexington, KY ### [SoC Power Flow Methodology Engineer](https://jobs.opennash.com/companies/apple/jobs/aa91cc89a2ee676c578b/) Apple · Austin, United States of America OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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