[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All NVIDIA jobs](https://jobs.opennash.com/companies/nvidia/) · [Search jobs](/search/) NVIDIA · Multiple locations # CPU Design Methodology Engineer Multiple locations Design Listed on NVIDIA’s official careers site. Posted September 22, 2026. Check that it is still open and apply there. [Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-OR-Hillsboro/CPU-Design-Methodology-Engineer_JR2023733) [OpenNash Jobs](https://jobs.opennash.com/) / [NVIDIA](https://jobs.opennash.com/companies/nvidia/) / CPU Design Methodology Engineer ## Job description We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. ### What you'll be doing - Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner - Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them - Own front-end design quality checks and reviews to present the physical design team with high-quality RTL What we need to see: A Masters in Computer or Electrical Engineering or equivalent experience - 8+ years of experience in chip design, specializing in SOC integration and design automation - Excellent analytical and problem-solving skills Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation - Strong coding skills in Perl, Python, or other industry-standard scripting languages Experience in synthesis and physical design is a plus Good interpersonal skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We employ some of the most forward-thinking and hardworking people in the world. Are you passionate about becoming a part of an outstanding team supporting the latest in CPU technology? If so, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until August 22, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. ## At a glance - Posted by the employer: Sep 22, 2026 - First seen by OpenNash: Aug 20, 2026 - Last checked: Oct 20, 2026 - Listed for: 61 days - Location: Multiple locations[Apply on NVIDIA’s careers site →](https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-OR-Hillsboro/CPU-Design-Methodology-Engineer_JR2023733) ## More jobs at NVIDIA ### [Senior Physical Design Methodology Engineer, Innovus Flows](https://jobs.opennash.com/companies/nvidia/jobs/094fde75a32fb5d6ad3f/) ### [Senior Physical Design and Timing Engineer](https://jobs.opennash.com/companies/nvidia/jobs/bfe435274c71ca1eed5c/) ### [Data Processing Developer Technology Intern - 2027](https://jobs.opennash.com/companies/nvidia/jobs/fce56c3df53f841621f5/) ### [Developer Relations Manager, Computer Aided Engineering](https://jobs.opennash.com/companies/nvidia/jobs/a5fa021dea0daaf10d7c/) ### [EDA Workflow Optimization Engineer](https://jobs.opennash.com/companies/nvidia/jobs/c987f8ab76243c5a6cfe/) ## Similar jobs at other companies ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/27bd54e804c3da2d6519/) Qualcomm · Bangalore, India ### [CPU SRAM Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/2766ec16a56a09aa6a85/) Qualcomm · Bangalore, India ### [Senior Staff Engineer Physical Design and Methodology (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/46bbe226ff31021fb81f/) Infineon Technologies · Munich ### [Staff Engineer Simulation and Package Design Methodology (f/m/div)](https://jobs.opennash.com/companies/infineon-technologies/jobs/c531842c5bdd1461c64a/) Infineon Technologies · Villach ### [Senior CPU Front End Methodology Engineer](https://jobs.opennash.com/companies/intel/jobs/0f80fa889812e174368a/) Intel OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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