[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Nokia jobs](https://jobs.opennash.com/companies/nokia/) · [Search jobs](/search/)

Nokia · Taiwan

# Analog Layout Engineer

Taiwan On-site Operations 

Listed on Nokia’s official careers site. Posted July 7, 2026. Check that it is still open and apply there.
[Apply on Nokia’s careers site →](https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/37609)

[OpenNash Jobs](https://jobs.opennash.com/) / [Nokia](https://jobs.opennash.com/companies/nokia/) / Analog Layout Engineer

## Job description

The successful candidate shall utilize advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent analog matching performance, area and power requirements. He or she shall will be working on the latest process technologies. He or she shall work closely with circuit designers to generate high-quality layout in a highly efficient way.

## Responsibilities

Work close with circuit designers to optimize the floor plan; Perform daily layout editing, DRC/LVS tasks to ensure the quality of the layout; Create a solid power grid for better power integrity; Work with the circuit designers to optimize the quality of the layout, including but not limited to matching and signal integrity; Employ efficient design methodologies to reduce the number of iterations and to deliver the product promptly.

## Qualifications

### Mandatory Knowledge/Skills/Abilities

Extremely familiar with layout editing tools, such as Virtuoso; Highly proficient with DRC/LVS/ERC related tools and flows, such as Calibre, PVS (or IC Validator); Have extensive experience designing layout in deep sub-micron CMOS technologies, especially FinFET technologies (7nm and 5nm); Decent understanding in the issues of electro-migration and IR drop, RC delay, self-heating, capacitive cross-talk, etc.; Decent understanding in analog layout requirements, such as matching and shielding; Knowledge in automatic P&R or chip-level floor planning and chip-level layout integration.

### Preferred Knowledge/Skill/Abilities

Decent Understanding in analog design methodologies, including the use of layout constraints; Knowledge in performing RC extraction and EM/IR analysis; Knowledge in CAD tool setup and maintenance; Ability to generate pCell and pyCell to facilitate layout design; Excellent communication skills and team spirit to work with members across multiple sites and functionalities; Experience in designing layout for high-speed, high-performance analog, and mixed-signal circuits.

### Education and Experience

Requirements: 5-10 years' experience in analog and mixed signal layout design. 歡迎身障求職者

## At a glance
- Posted by the employer: Jul 7, 2026
- First seen by OpenNash: Oct 13, 2026
- Last checked: Oct 20, 2026
- Listed for: 105 days
- Location: Taiwan
- Work arrangement: On-site[Apply on Nokia’s careers site →](https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/37609)

## More jobs at Nokia

### [Analog/Mixed Signal Design Engineer](https://jobs.opennash.com/companies/nokia/jobs/c6bf0ed0636a3186bc5d/)

Taiwan

### [4LS Support Engineer](https://jobs.opennash.com/companies/nokia/jobs/95cdee4c7b3f63912975/)

India

### [AI & Business Process Transformation Trainee](https://jobs.opennash.com/companies/nokia/jobs/05393fe3e40282dd4007/)

Portugal

### [AI Engineering Co-op](https://jobs.opennash.com/companies/nokia/jobs/3c1a92d37cd96cd30ef7/)

United States

## Similar jobs at other companies

### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/dae39b856c85418d4dfc/)

Infineon Technologies · Hanoi

### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/a6206d71c9dd6693d96d/)

Infineon Technologies · Penang

### [Analog Layout Engineer - FinFET Technology](https://jobs.opennash.com/companies/capgemini/jobs/2247f120d925b6aebc25/)

Capgemini · Ampelokipoi, Athens, Thessaloniki/Steliou Kazantzidi

### [Senior Analog Mixed-Signal IC Layout Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/221d9e3fe5624daf8663/)

Astera Labs · Singapore City

### [Senior Analog Layout Engineer](https://jobs.opennash.com/companies/ciena/jobs/1620135583ef2d96079e/)

Ciena · Ottawa +1 more

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)