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Nokia · United States

# Senior ATE Wafer Test Engineer

United States Hybrid Senior individual contributor Operations 

Listed on Nokia’s official careers site. Posted April 15, 2026. Check that it is still open and apply there.
[Apply on Nokia’s careers site →](https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/33975)

[OpenNash Jobs](https://jobs.opennash.com/) / [Nokia](https://jobs.opennash.com/companies/nokia/) / Senior ATE Wafer Test Engineer

## Job description

### Description

Sr Analog Wafer Level ATE Test Engineer to support existing IC ATE development and production Experience with Analog ATE wafer sort testing and STDF data handling is required. Knowledge of automated test equipment (ATE) platforms, probe card development, software and hardware for wafer level testing. The candidate is expected to have hands on experience with NPI test development, WS production yield analysis and yield drop out debug and disposition.

Familiar & comfortable with high-performance medium volume ASICs, production environment Ability to write status reports, schedules and project plans and present results in general meeting formats. Capable to contact vendors for project schedule, testing status, booking equipment, and test debugging Collection, analysis, correlation and interpretation of data using statistical techniques and industry standard tools is required Some experience with scripting and simple programming skills.

Critical thinking skills to debug and solve problems required Experienced with scheduling and planning projects with external vendors and customers RF ATE testing experience is a plus

## Responsibilities

### Responsibilities

Interface with external vendors for R&D and production testing
- Ensure and correlate test SW and HW to written Test Plan Production yield tracking, milestone tracking, problem assessment/disposition and invoice tracking Wafer level ATE platform support of production, yield analysis, failure Paretos and yield improvement Production logistics including ASIC wafer tracking and travelers Supporting engineering releases through pilot runs and production
- Develop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards

## Qualifications

### Experience

Required: BS EE/physics with 5+ years industrial experience Analog wafer level IC testing
- Must have experience with probe card cleaning, maintenance and debug
- Must have experience with ATE platform and wafer prober setup and operation
- Must be able to assemble coherent and concise reports summarizing status and next steps
- Must be able to effectively present findings to a cross-functional, collaborative team environment Prefer experience with Galaxy or JMP data analysis tools.

Prefer Advantest 93K expertise including calibration, TL/ISO compliance and ESD compliance Prefer expertise with Perl, VB, SQL and Perforce Prefer UNIX/Linux experience Skills Required:
- Proficient interacting with design and application engineers
- Strong debug and analytical skills Self-motivated team player
- Strong time and project management skills Detail oriented with all aspects of technical work and vendor interactions
- Excellent verbal and written communication skills

## At a glance
- Posted by the employer: Apr 15, 2026
- First seen by OpenNash: Oct 13, 2026
- Last checked: Oct 20, 2026
- Listed for: 188 days
- Location: United States
- Work arrangement: Hybrid[Apply on Nokia’s careers site →](https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/33975)

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