[Skip to main content](#main-content)

[ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/)

Microsoft

# Principal Silicon Design Verification Engineer

United States, California, Santa Clara, Mountain View, Oregon, Hillsboro, Texas, Austin, Idaho, Boise, San Diego, Washington, Redmond Senior individual contributor Design 

Listed on Microsoft’s official careers site. Posted October 20, 2026. Check that it is still open and apply there.
[Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556870474)

[OpenNash Jobs](https://jobs.opennash.com/) / [Microsoft](https://jobs.opennash.com/companies/microsoft/) / Principal Silicon Design Verification Engineer

## Job description

Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP) Develop Test
- Plan and write unit tests for functional validation
- Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA Experience with Cluster, SoC, or Fullchip level verification Prior verification experience with PCIe, both at the Transaction and Data Link Layer Strong proficiency in Verilog, System Verilog, and UVM based testbench environment. Good understanding of computer architecture and digital design fundamentals Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to succesfull tapeout.

## At a glance
- Posted by the employer: Oct 20, 2026
- First seen by OpenNash: Aug 21, 2026
- Last checked: Nov 1, 2026
- Listed for: 72 days
- Location: United States, California, Santa Clara, Mountain View, Oregon, Hillsboro, Texas, Austin, Idaho, Boise, San Diego, Washington, Redmond[Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556870474)

## Hiring at Microsoft
- Open jobs: 2,199
- New in the last 7 days: After two weekly collections
- Tracked since: Jul 10, 2026

[All Microsoft jobs](https://jobs.opennash.com/companies/microsoft/) · [Weekly hiring report](/reports/hiring/)

## More jobs at Microsoft

### [Associate Creative Director, Art & Film](https://jobs.opennash.com/companies/microsoft/jobs/33d9c9ae5297dd195f2e/)

United States, Washington, Redmond, California, Mountain View

### [Creative Technologist](https://jobs.opennash.com/companies/microsoft/jobs/6fd6db5aba1bcfd2c626/)

United States, Washington, Redmond, California, Mountain View, New York

### [Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/5dea08a06db04d071bf3/)

United States, Washington, Redmond, California, Mountain View

### [Design Manager](https://jobs.opennash.com/companies/microsoft/jobs/b6d62e77ace2e6a93386/)

Singapore

### [Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/f59f04420880bd44e8b9/)

United States, North Carolina, Raleigh

## Similar jobs at other companies

### [Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)](https://jobs.opennash.com/companies/bae-systems/jobs/a2d0fcd796f42768f03a/)

BAE Systems · Nashua, New Hampshire, United States

### [Senior Staff Engineer Pre-Silicon Verification AMS](https://jobs.opennash.com/companies/infineon-technologies/jobs/b1b1acf8bd970c896378/)

Infineon Technologies · Austin, TX, Andover, MA, USA, Warwick, RI

### [ASIC Engineering Intern, Design Verification (Silicon Engineering)](https://jobs.opennash.com/companies/meta-platforms/jobs/7b1bfa7f54cd3cee30b0/)

Meta Platforms · Sunnyvale, CA

### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/)

Qualcomm · Tijuana, Baja California, Mexico

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

[ OpenNash ](https://opennash.com/)

AI-native services firm that builds custom software and 24/7 AI agents.

OpenNash Jobs is an OpenNash Applied AI project.
[Book time with OpenNash](https://calendly.com/opennash/new-meeting?hide_gdpr_banner=1)

Jobs
- [Search jobs](https://jobs.opennash.com/search/)
- [Companies](https://jobs.opennash.com/explore/)
- [Hiring report](https://jobs.opennash.com/reports/hiring/)
- [AI assistants](https://jobs.opennash.com/connect/)
- [How it works](https://jobs.opennash.com/methodology/)

OpenNash
- [opennash.com](https://opennash.com/)
- [Services](https://opennash.com/ai-agent-consulting/)
- [OpenNash CX](https://opennash.com/cx/)
- [AI Tools](https://opennash.com/ai-tools/)
- [Blog](https://opennash.com/blog/)
- [About](https://opennash.com/about/)

Contact
- [hello@opennash.com](mailto:hello@opennash.com)

- [LinkedIn](https://www.linkedin.com/company/opennash)

- [Support](https://jobs.opennash.com/support/)

- [Privacy](https://jobs.opennash.com/privacy/)

- [Terms](https://jobs.opennash.com/terms/)

© 2026 OpenNash, Inc. Company names and public job postings belong to their respective owners. Employers control source availability and application decisions.
