[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Microsoft # Principal Silicon Design Verification Engineer United States, California, Santa Clara, Mountain View, Oregon, Hillsboro, Texas, Austin, Washington, Redmond Senior individual contributor Design Listed on Microsoft’s official careers site. Posted October 20, 2026. Check that it is still open and apply there. [Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556870706) [OpenNash Jobs](https://jobs.opennash.com/) / [Microsoft](https://jobs.opennash.com/companies/microsoft/) / Principal Silicon Design Verification Engineer ## Job description As a Principal Engineer - ASIC verification in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career. As a Principal Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter. - Lead key components of functional validation of complex ASIC SOC using UVM/C test bench - Perform pre-silicon SoC verification, post-silicon validation by defining testing strategies - Work with cross functional teams, architecture, design, verification, partner teams for project execution and influence next generation designs - Develop test plan, C tests and infrastructure to complete functional validation of complex design and report bug/issues Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals Actively participate in chip bring up and write test firmware to support various teams Innovate to improve validation efficiency through methodologies and tools - Coach and mentor others in your areas of expertise Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. 10+ years of experience in pre-silicon validation with a proven track record of delivering high performance Network switches/accelerators, Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU's) or relevant experience. Experience in UVM/C verification methodology Knowledge of Ethernet, TCP/IP, ROCEv2, MAC/PCS, Networking NIC/Switches. Proven track record with the definition and development of complex SoCs. In depth understanding of processors and peripheral interconnect bus protocols and architectures Strong proficiency in Verilog, System Verilog, and UVM based testbench environment. Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to successful tapeout. ## At a glance - Posted by the employer: Oct 20, 2026 - First seen by OpenNash: Jul 17, 2026 - Last checked: Nov 1, 2026 - Listed for: 107 days - Location: United States, California, Santa Clara, Mountain View, Oregon, Hillsboro, Texas, Austin, Washington, Redmond[Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556870706) ## Hiring at Microsoft - Open jobs: 2,199 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Microsoft jobs](https://jobs.opennash.com/companies/microsoft/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Microsoft ### [Associate Creative Director, Art & Film](https://jobs.opennash.com/companies/microsoft/jobs/33d9c9ae5297dd195f2e/) United States, Washington, Redmond, California, Mountain View ### [Creative Technologist](https://jobs.opennash.com/companies/microsoft/jobs/6fd6db5aba1bcfd2c626/) United States, Washington, Redmond, California, Mountain View, New York ### [Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/5dea08a06db04d071bf3/) United States, Washington, Redmond, California, Mountain View ### [Design Manager](https://jobs.opennash.com/companies/microsoft/jobs/b6d62e77ace2e6a93386/) Singapore ### [Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/f59f04420880bd44e8b9/) United States, North Carolina, Raleigh ## Similar jobs at other companies ### [Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)](https://jobs.opennash.com/companies/bae-systems/jobs/a2d0fcd796f42768f03a/) BAE Systems · Nashua, New Hampshire, United States ### [Senior Staff Engineer Pre-Silicon Verification AMS](https://jobs.opennash.com/companies/infineon-technologies/jobs/b1b1acf8bd970c896378/) Infineon Technologies · Austin, TX, Andover, MA, USA, Warwick, RI ### [ASIC Engineering Intern, Design Verification (Silicon Engineering)](https://jobs.opennash.com/companies/meta-platforms/jobs/7b1bfa7f54cd3cee30b0/) Meta Platforms · Sunnyvale, CA ### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/) Qualcomm · Tijuana, Baja California, Mexico OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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