[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Microsoft jobs](https://jobs.opennash.com/companies/microsoft/) · [Search jobs](/search/) Microsoft # Senior Silicon Design Verification Engineer United States, California, Mountain View Senior individual contributor Design Listed on Microsoft’s official careers site. Posted October 12, 2026. Check that it is still open and apply there. [Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556962139) [OpenNash Jobs](https://jobs.opennash.com/) / [Microsoft](https://jobs.opennash.com/companies/microsoft/) / Senior Silicon Design Verification Engineer ## Job description The candidate for this position will be expected and able to complete the following responsibilities: Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors. Extend the compile and build flow to support custom firmware-style tests. Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files. Design additional custom FPGA RTL for protocol interfaces and feature enablement. Release stable platforms to the firmware team and keep them working as the design evolves. Develop and extend custom python tooling to interface with the FPGA platform. Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware, and security teams. Root-cause failing post-silicon tests to closure, collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs, coordinating cross-team debug, and delivering fixes such as handling fatal errors, correcting driver access violations, and reconciling registers modified by boot firmware. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Experience developing C and C++ test content for subsystem and SoC verification, including bare-metal and firmware-style tests, with working knowledge of SystemVerilog testbenches. Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx), including board images, platform tooling, and testbench changes that enable firmware and validation teams. Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters Experience owning pre-silicon verification of IP, subsystems, or SoCs through the full cycle, including test planning, test development, failure debug, and coverage signoff. Experience with post-silicon bring-up and validation, including running test suites on silicon and debugging boot, platform, and connectivity issues in a lab environment. Proficiency in Python, or a similar scripting language such as Perl or Ruby, for test automation, build flows, and log or data parsing. In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs. Experience with low-level and embedded software, including assembly, startup code, linker scripts, and Makefile-based build flows. Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB. Experience collaborating across architecture, design, firmware, and validation teams, with strong communication skills. Understanding of silicon and/or computer architecture. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. ## At a glance - Posted by the employer: Oct 12, 2026 - First seen by OpenNash: Aug 21, 2026 - Last checked: Oct 18, 2026 - Listed for: 58 days - Location: United States, California, Mountain View[Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556962139) ## More jobs at Microsoft ### [Business Operations Coordinator, Microsoft AI](https://jobs.opennash.com/companies/microsoft/jobs/36b72631a00869ccebe8/) United States, California, Mountain View ### [Business Program Manager - AI Infrastructure](https://jobs.opennash.com/companies/microsoft/jobs/80438a91e536e388b7d6/) United States, California, Mountain View ### [Principal Mechanical Engineer - AI Systems](https://jobs.opennash.com/companies/microsoft/jobs/43a67da8bed523038c50/) United States, California, Mountain View ### [Principal Software Engineer - AI Infrastructure Engineering Systems](https://jobs.opennash.com/companies/microsoft/jobs/95bb5189a92d36291798/) United States, California, Mountain View ### [Principal Software Engineer - Systems and Infrastructure](https://jobs.opennash.com/companies/microsoft/jobs/d4997df36192b249514b/) United States, California, Mountain View ## Similar jobs at other companies ### [Senior Staff Engineer Pre-Silicon Verification AMS](https://jobs.opennash.com/companies/infineon-technologies/jobs/b1b1acf8bd970c896378/) Infineon Technologies · Austin, TX, Andover, MA, USA, Warwick, RI ### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/) Qualcomm · Tijuana, Baja California, Mexico ### [Design Verification Engineer, Silicon](https://jobs.opennash.com/companies/meta-platforms/jobs/7f93c1751ac77c7a2081/) Meta Platforms · Sunnyvale, CA +3 more ### [Mechanical Engineer Design Verification Checker](https://jobs.opennash.com/companies/lockheed-martin/jobs/4e7ba518aa7393e46d7a/) Lockheed Martin · Englewood, CO, Littleton OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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