[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Microsoft jobs](https://jobs.opennash.com/companies/microsoft/) · [Search jobs](/search/) Microsoft # Principal Physical Design Engineer United States, Washington, Redmond, California, Mountain View, Santa Clara, Oregon, Hillsboro, Texas, Austin, Idaho, Boise, North Carolina, Raleigh Senior individual contributor Design Listed on Microsoft’s official careers site. Posted October 12, 2026. Check that it is still open and apply there. [Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556933623) [OpenNash Jobs](https://jobs.opennash.com/) / [Microsoft](https://jobs.opennash.com/companies/microsoft/) / Principal Physical Design Engineer ## Job description If hired, you will be responsible for delivering TFM (tool, flow and methodology) of Physical Design tasks at block, sub-chip, and/or full-chip level. The roles include one or more of the following tasks - Place and Route (PnR), Static Timing Analysis (STA) and timing ECOs, Physical Verification (PV), Formal Equivalency Verification (FEV), Functional ECO, Global Clocking Construction, IR-Drop/EM (EMIR) and PD Infrastructure and IPs collaterals handling with details below: - Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level - Develop and implement methodologies and strategies to improve physical design efficiency and performance - Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing analysis, physical verification, functional logics equivalence, low power verification and electromigration and IR drop Implementation of functional and timing ECO with least physical design impact - Design and implement the global clocking scheme at SOC and sub chip levels - Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies Installation and quality check of internal and external IP collaterals for use by Physical - Design execution team Conduct physical design reviews, identify and resolve design issues, and provide guidance to engineers. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. ### Other This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Bachelor's or Master's in Electrical or Computer Engineering or related field with 10+ years of experience Experience in tapeouts of complex ASICs in leading edge technology 10+ years of experience in blocks level place and route Expertise in one or more of physical design EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus; Siemens Calibre. Understanding of semiconductor design principles, methodologies, and tools. Proven track record of successfully leading physical design projects and delivering high-quality semiconductor products Adequate scripting skillsets in TCL and Python Good understanding of foundry tech files and rule decks ## At a glance - Posted by the employer: Oct 12, 2026 - First seen by OpenNash: Jul 17, 2026 - Last checked: Oct 18, 2026 - Listed for: 93 days - Location: United States, Washington, Redmond, California, Mountain View, Santa Clara, Oregon, Hillsboro, Texas, Austin, Idaho, Boise, North Carolina, Raleigh[Apply on Microsoft’s careers site →](https://apply.careers.microsoft.com/careers/job/1970393556933623) ## More jobs at Microsoft ### [Associate Creative Director, Art & Film](https://jobs.opennash.com/companies/microsoft/jobs/33d9c9ae5297dd195f2e/) United States, Washington, Redmond, California, Mountain View ### [Creative Director, Art & Film](https://jobs.opennash.com/companies/microsoft/jobs/24d2e1b5e41ee5c14772/) United States, California, Mountain View, Washington, Seattle ### [Creative Director, Copy - Windows, Surface & Services](https://jobs.opennash.com/companies/microsoft/jobs/0b6be9f3cf6548eea132/) United States, Washington, Redmond, California, Mountain View ### [Creative Director, Design](https://jobs.opennash.com/companies/microsoft/jobs/ac15d74d54b21dd4881a/) United States, California, Mountain View, Washington, Redmond ### [Creative Technologist](https://jobs.opennash.com/companies/microsoft/jobs/6fd6db5aba1bcfd2c626/) United States, Washington, Redmond, California, Mountain View, New York ## Similar jobs at other companies ### [Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/dda9e8d7a67c5354a6eb/) Qualcomm · Tijuana, Baja California, Mexico ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/831567c9a5b68f024d18/) Qualcomm · Austin, Texas, United States of America ### [Physical Design Engineer II (IC)](https://jobs.opennash.com/companies/arrow-electronics/jobs/ec91eccc72f42a5fcfc2/) Arrow Electronics · San Jose, CA, United States of America ### [Circuit Design Engineer, Principal](https://jobs.opennash.com/companies/lockheed-martin/jobs/78cd34d8da60b7b89600/) Lockheed Martin · Goleta, CA ### [Principal Product Design Engineer](https://jobs.opennash.com/companies/comfort-systems-usa/jobs/6973033b0f66ed1f6420/) Comfort Systems USA · Indianapolis, IN [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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