[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Meta Platforms jobs](https://jobs.opennash.com/companies/meta-platforms/) · [Search jobs](/search/) Meta Platforms · Sunnyvale, CA # Silicon Packaging Technology Engineer Sunnyvale, CA Operations Listed on Meta Platforms’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1540138954552904/) [OpenNash Jobs](https://jobs.opennash.com/) / [Meta Platforms](https://jobs.opennash.com/companies/meta-platforms/) / Silicon Packaging Technology Engineer ## Job description Reality Labs is delivering Meta's vision through AI-powered wearable products. The compute performance, power efficiency, and form factor requirements demand custom silicon with cutting-edge packaging solutions. We are seeking a Silicon Packaging Technology Engineer to join our team and drive advanced packaging technology from concept through productization for next-generation consumer hardware. ## Responsibilities - Lead development and roadmap creation for advanced and disruptive packaging technologies (hybrid bonding, TSV, fan-out, SiP, flip chip, SMT, solder ball attach, and assembly processes) - Establish and manage relationships with foundries, OSATs, substrate suppliers, and material suppliers to support package development activities - Influence and align OSAT and foundry partners' roadmaps with Meta's custom silicon packaging roadmap - Collaborate cross-functionally with internal teams (silicon design, architecture, system, thermal, mechanical) and external partners (design houses, OSATs, substrate vendors) to ensure manufacturability, integration, and reliability - Support test vehicle (TV) design, process feasibility, simulation, and design rule/DFM checks with emphasis on thermo-mechanical reliability Drive - Design of Experiments (DOEs) for initial builds, product qualification, and sustaining activities - Lead triage efforts for unexpected inline process, equipment, and quality issues; drive root cause failure analysis (FA) and corrective actions with partners - Evaluate and address chip-package interaction (CPI) effects, board-level reliability (BLR), and component-level reliability (CLR) through simulation, testing, and data analysis - Track technology gaps, reliability risks, and yield issues; compile and maintain POR, TOR, FMEA, and related KPIs - Stay updated on advanced packaging technologies and market trends and identify emerging technologies Travel both domestically and internationally up to 10% of the time ## Qualifications - Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience - 12+ years of experience in advanced silicon packaging development, process integration, and manufacturing - Ability to work with mechanical and thermal constraints to co-optimize package architecture for demanding form factors - Demonstrated cross-functional collaboration with internal teams and external partners (foundry, OSAT, substrate vendors, ODMs) Experience taking products from concept to prototyping and production, including manufacturing specifications, vendor qualifications, and yield/cost optimization - Bachelor's degree in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a relevant technical field - Master's or PhD degree in a relevant engineering discipline Experience with board-level and component-level reliability testing and qualification (JEDEC standards) Strong DOE methodology, statistical data analysis, and process characterization skills Experience driving failure analysis (FA) — including physical FA techniques, fault isolation, and root cause determination - Excellent problem-solving and communication skills; the ability to influence cross-functional stakeholders - Track record of successful complex package product qualification with OSATs Experience with a broad range of packaging technologies: WLCSP, fan-out RDL, WoW, CoW, PoP, SiP, flip chip, and 3D stacking - Strong understanding of chip-package interaction (CPI), thermo-mechanical stress, and warpage management - Ability to work independently, manage multiple programs, and travel internationally (typically once per quarter) ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Sunnyvale, CA[Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1540138954552904/) ## More jobs at Meta Platforms ### [ASIC Implementation Engineer, Static Verification](https://jobs.opennash.com/companies/meta-platforms/jobs/46a040a0490f25af7852/) Sunnyvale, CA ### [ASIC Validation Engineer, Network Validation & Characterization](https://jobs.opennash.com/companies/meta-platforms/jobs/6f84a078ca80d8b450aa/) Sunnyvale, CA ### [ASIC Validation Engineer, Power Validation & Characterization](https://jobs.opennash.com/companies/meta-platforms/jobs/5d9ce53662d093a0f5eb/) Sunnyvale, CA ### [Audio Electrical Engineer](https://jobs.opennash.com/companies/meta-platforms/jobs/e6f5299cb79393a83514/) Sunnyvale, CA ### [CAD and Integration Engineer, Silicon](https://jobs.opennash.com/companies/meta-platforms/jobs/30ceb2a5b1665f8ae267/) Sunnyvale, CA ## Similar jobs at other companies ### [Silicon Packaging Design Engineer](https://jobs.opennash.com/companies/intel/jobs/7077966f9f2a2582e90f/) Intel · US, Arizona, Phoenix ### [Package Layout Design Engineer, Annapurna Labs - AI Silicon Packaging](https://jobs.opennash.com/companies/amazon/jobs/e1b91186671919c7b539/) Amazon · US, AZ, Tempe ### [Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging](https://jobs.opennash.com/companies/amazon/jobs/e09de732a6619b1d92ed/) Amazon · US, TX, Austin ### [Silicon Test Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/34df508b8339324e1472/) Qualcomm · Tijuana, Baja California, Mexico ### [Silicon Test Engineer (Digital)](https://jobs.opennash.com/companies/qualcomm/jobs/465dd9e94c5f6e1bb6e1/) Qualcomm · Tijuana, Baja California, Mexico OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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