[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Meta Platforms jobs](https://jobs.opennash.com/companies/meta-platforms/) · [Search jobs](/search/)

Meta Platforms · Sunnyvale, CA +1 more

# ASIC Engineer, Foundry and IP

Sunnyvale, CA +1 more Operations 

Listed on Meta Platforms’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/2247983762446649/)

[OpenNash Jobs](https://jobs.opennash.com/) / [Meta Platforms](https://jobs.opennash.com/companies/meta-platforms/) / ASIC Engineer, Foundry and IP

## Job description

Meta is building custom silicon to power the next generation of AI infrastructure and immersive computing experiences. The Infrastructure Silicon team is responsible for designing and delivering high-performance, power-efficient ASICs that underpin Meta's data center and AI workloads. We are looking for individuals with experience in foundry technology benchmarking and PPA analysis, stdcell circuit design and characterization, memory compiler PPA optimization and test chip design and testing.

## Responsibilities
- Analyze and benchmark foundry process offering with physical design teams to identify optimal technologies for product roadmaps
- Drive early PPA evaluation of foundation IP drops by running preliminary PnR experiments to identify issues and opportunities for improvement Architect, design, and characterize high-performance, low-power, and ultra-high-density standard cell libraries with foundry partners and Physical design teams
- Run transistor-level simulations (SPICE), direct custom physical layouts, and manage automated library characterization flows
- Evaluate, benchmark, and choose third-party memory compilers (SRAM, Register Files, ROM) based on rigorous PPA and trade-off metrics
- Participate in physical implementation, and tape-out of silicon test chips targeted at proving out new foundation IP, custom structures

## Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 6+ years of experience in a foundry team driving PPA analysis and engineering army benchmarking Deep understanding of CMOS device physics, digital circuit design, and advanced node layout constraints
- Proven track record of participating in test chip tapeouts.

Hands-on experience in owning end to end design and sign-off of partitions on a test chip Expert-level command of design environments like Cadence Virtuoso, HSPICE, Spectre Working knowledge of synthesis, PnR, STA and PDV tools to converge a block on a test chip High proficiency in scripting with Python, TCL, Perl, or SKILL to automate large-scale evaluation pipelines and data analysis MS or

PhD in electrical engineering 8+ years of experience driving PPA analysis, selection and optimization of foundational IPs - Standard cells and memory compilers in particular Experience owning test chips as chip lead is preferred Experience driving DTCO optimization with foundry partners and design teams on advanced logic technologies is preferred

Experience in bringing multiple sub-5nm, 3nm, or 2nm GAA (Gate-All-Around) complex test chips from initial architecture through to validation

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days
- Location: Sunnyvale, CA +1 more[Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/2247983762446649/)

## More jobs at Meta Platforms

### [ASIC Engineer Intern, Architecture](https://jobs.opennash.com/companies/meta-platforms/jobs/2863c97e72eed2694acb/)

Sunnyvale, CA +1 more

### [ASIC Engineer, Architecture Kernel Development](https://jobs.opennash.com/companies/meta-platforms/jobs/112436cfade49be097c7/)

Sunnyvale, CA +1 more

### [ASIC Engineer, Implementation - Timing](https://jobs.opennash.com/companies/meta-platforms/jobs/42149fe1f3ebacef1ed2/)

Sunnyvale, CA +1 more

### [ASIC Engineer, Performance Architecture and Modeling](https://jobs.opennash.com/companies/meta-platforms/jobs/db2725173e3d52120cdf/)

Sunnyvale, CA +1 more

### [ASIC Engineer, Power](https://jobs.opennash.com/companies/meta-platforms/jobs/c096c85f7543528786fb/)

Sunnyvale, CA +1 more

## Similar jobs at other companies

### [Principal Software Engineer - CoreAI (Foundry Observability)](https://jobs.opennash.com/companies/microsoft/jobs/5bb71416b2ef5139f80c/)

Microsoft · United States, Washington, Redmond

### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/)

Lockheed Martin · Liverpool, NY

### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/)

Lockheed Martin · Boulder, CO

### [ASIC Timing and Methodology Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/9a3a66e840e1ae3025fb/)

Qualcomm · Tijuana, Baja California, Mexico

[Operations jobs](/functions/operations/)

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)