[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Meta Platforms jobs](https://jobs.opennash.com/companies/meta-platforms/) · [Search jobs](/search/) Meta Platforms · Sunnyvale, CA +3 more # Physical Design Engineer, Reality Labs Silicon Sunnyvale, CA +3 more Design Listed on Meta Platforms’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1600351258480710/) [OpenNash Jobs](https://jobs.opennash.com/) / [Meta Platforms](https://jobs.opennash.com/companies/meta-platforms/) / Physical Design Engineer, Reality Labs Silicon ## Job description Meta's Silicon Engineering team is building custom silicon to power the next generation of virtual and augmented reality products, including VR headsets and AR glasses. As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. In this role, you will collaborate closely with architecture, design, and verification teams to shape the physical implementation strategy for wearable and spatial computing devices that define the future of human connection. ## Responsibilities - Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification - Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products - Perform static timing analysis and timing closure across multiple process corners and operating conditions - Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off - Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions - Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements - Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes - Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization - Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency ## Qualifications - Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience - 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off - 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below) Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent Experience with physical verification flows including DRC, LVS, and antenna sign-off Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis Experience with physical design implementation tools such as Synopsys Fusion Compiler (including FusionPilot/ConfigAI for run analysis and TCL configuration), Cadence Innovus, StarRC, and PrimeTime Experience with physical design for low-power wearable or mobile SoCs, including multi-voltage domain and power gating implementation Experience developing and maintaining physical design automation scripts using Python or Tcl to improve implementation flows - Familiarity with co-design methodologies that bridge RTL microarchitecture decisions and physical implementation constraints Experience with advanced node process design kits (5nm or below) and associated physical design challenges ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Sunnyvale, CA +3 more[Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1600351258480710/) ## More jobs at Meta Platforms ### [Design Verification Engineer, Silicon](https://jobs.opennash.com/companies/meta-platforms/jobs/7f93c1751ac77c7a2081/) Sunnyvale, CA +3 more ### [GFX/Display IP Digital Design Engineer](https://jobs.opennash.com/companies/meta-platforms/jobs/15bdf6a0665cc93a0d52/) Sunnyvale, CA +3 more ### [SOC Architect, Reality Labs Silicon](https://jobs.opennash.com/companies/meta-platforms/jobs/ee139d1338b228739c59/) Sunnyvale, CA +3 more ### [Silicon Performance Architect, Reality Labs](https://jobs.opennash.com/companies/meta-platforms/jobs/2bc9075ff3c69f3c1a28/) Sunnyvale, CA +3 more ### [Silicon Power Architect, Reality Labs](https://jobs.opennash.com/companies/meta-platforms/jobs/da21c0f7aedb40ffd64a/) Sunnyvale, CA +3 more ## Similar jobs at other companies ### [Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/dda9e8d7a67c5354a6eb/) Qualcomm · Tijuana, Baja California, Mexico ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/831567c9a5b68f024d18/) Qualcomm · Austin, Texas, United States of America ### [Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/c6f51a8f2a250a28e52f/) Microsoft · United States, Oregon, Hillsboro, California, Mountain View, North Carolina, Raleigh ### [Physical Design Engineer II (IC)](https://jobs.opennash.com/companies/arrow-electronics/jobs/ec91eccc72f42a5fcfc2/) Arrow Electronics · San Jose, CA, United States of America ### [Senior Physical Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/e7e19400d6681015759d/) Microsoft · United States, Oregon, Hillsboro, California, Mountain View, Texas, Austin, North Carolina, Raleigh, Washington, Redmond [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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