[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Meta Platforms jobs](https://jobs.opennash.com/companies/meta-platforms/) · [Search jobs](/search/) Meta Platforms · Sunnyvale, CA # ASIC Engineering Intern, Design Verification (Silicon Engineering) Sunnyvale, California, US Internship or early career Early career Design Listed on Meta Platforms’s official careers site. Posted October 14, 2026. Check that it is still open and apply there. [Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1079763448023260/) [OpenNash Jobs](https://jobs.opennash.com/) / [Meta Platforms](https://jobs.opennash.com/companies/meta-platforms/) / ASIC Engineering Intern, Design Verification (Silicon Engineering) ## Job description We are a team of engineers building the silicon IP that powers Augmented Reality (AR) glasses. Our focus is digital design for computer vision and image signal processing: high-performance, low-power hardware that fits into the tight power and space budget of a pair of eyeglasses. Our IP ships in several chips, and our roadmap covers products that will reach the market years from now. Meta is looking for a Design Verification intern to join our Silicon Accelerators team. You'll work with design, verification, and methodology engineers to verify vision and image-processing IP. You'll write test benches, plan and run tests, and track down bugs in both the design and the test environment. We're looking for someone who likes breaking things and figuring out why they broke. The internship is meant to give you real, production-level DV experience so you're ready to join full-time as a University Grad Design Verification Engineer. ## Responsibilities - Write SystemVerilog test benches and tests that verify digital IP blocks in computer vision and image signal processing pipelines - Build and extend UVM-based verification components (sequences, drivers, monitors, scoreboards) under the guidance of senior engineers Read design specifications and help write verification test plans, including stimulus, checks, and coverage goals - Run simulations, debug failures, and work out whether each bug is in the design (RTL) or the test bench - Track functional and code coverage, and write directed and constrained-random tests to close coverage gaps Write Python scripts to automate regressions, triage results, and improve verification workflows - Work with design and methodology engineers, and present your results in team reviews ## Qualifications Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field Coursework or project experience in digital logic design: logic gates, flip-flops, finite state machines, timing, and clock domains Experience with Verilog or SystemVerilog through coursework, labs, or projects Programming experience in an object-oriented language (e.g., SystemVerilog classes, C++, Python, or Java) Scripting experience in Python - Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment Intent to return to full-time degree program after completion of the internship Exposure to UVM (Universal Verification Methodology) or another class-based verification methodology - Familiarity with verification concepts such as constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding Coursework or projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration Hands-on experience with an RTL simulator (e.g., VCS, Xcelium, Questa, or Verilator) and waveform debugging - Knowledge of data structures and algorithms A completed digital design or verification project, such as a processor, memory controller, bus or communication interface, or FPGA design - Strong debugging instincts, curiosity, and clear communication ## At a glance - Posted by the employer: Oct 14, 2026 - First seen by OpenNash: Oct 18, 2026 - Last checked: Oct 18, 2026 - Listed for: 4 days - Location: Sunnyvale, California, US - Employment type: Internship or early career[Apply on Meta Platforms’s careers site →](https://www.metacareers.com/jobs/1079763448023260/) ## More jobs at Meta Platforms ### [ASIC Design Engineer Intern](https://jobs.opennash.com/companies/meta-platforms/jobs/9572236746cc52bf1edc/) Sunnyvale, California, US ### [Computer Vision Engineer Intern, Advanced Manufacturing (Reality Labs)](https://jobs.opennash.com/companies/meta-platforms/jobs/ab0609add66b2ab7682d/) Sunnyvale, California, US ### [Display Engineering Intern](https://jobs.opennash.com/companies/meta-platforms/jobs/9d427931b432089dfb92/) Sunnyvale, California, US ### [Manufacturing Test Engineering Intern, AI](https://jobs.opennash.com/companies/meta-platforms/jobs/1df97b6dff63eb1a179d/) Sunnyvale, California, US ### [Manufacturing Test Engineering Intern, Field Requirements & Feedback](https://jobs.opennash.com/companies/meta-platforms/jobs/2c0a6886c71525fef9eb/) Sunnyvale, California, US ## Similar jobs at other companies ### [ASIC Design Verification Engineer (Santa Clara, CA)](https://jobs.opennash.com/companies/qualcomm/jobs/ff2a97a9facc09977ec8/) Qualcomm · Santa Clara, California, United States of America ### [ASIC & FPGA Design Engineering Asc Mgr - L4](https://jobs.opennash.com/companies/lockheed-martin/jobs/8ca0594c2d9465c81092/) Lockheed Martin · King of Prussia, PA ### [ASIC & FPGA Design Engineering Asc Mgr - L4](https://jobs.opennash.com/companies/lockheed-martin/jobs/30b28ae3e787a3bf073f/) Lockheed Martin · Denver, CO, Sunnyvale, CA, Highlands Ranch ### [ASIC Verification/Design Engineering Intern](https://jobs.opennash.com/companies/hewlett-packard-enterprise/jobs/45311fe196502bca4238/) Hewlett Packard Enterprise · Roseville, California, United States of America ### [SOC Design Verification Engineer– Pre-Si/Post-Si Verification](https://jobs.opennash.com/companies/qualcomm/jobs/52cd325798071ca28842/) Qualcomm · Tijuana, Baja California, Mexico [Jobs in Sunnyvale, CA](/locations/us/ca/sunnyvale/)[Jobs in California](/locations/us-ca/)[Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)