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MediaTek · HsinChu

# <Data Center> Datacenter Compute SoC Architect

HsinChu Data & Analytics 

Listed on MediaTek’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there.
[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804002)

[OpenNash Jobs](https://jobs.opennash.com/) / [MediaTek](https://jobs.opennash.com/companies/mediatek/) / <Data Center> Datacenter Compute SoC Architect

## Job description

### Role Summary

We are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition, design, and optimization of our next-generation high-performance computing SoCs. In this critical role, you will be responsible for defining the system-on-chip architecture for scalable datacenter processors, balancing Power, Performance, and Area (PPA) constraints while meeting aggressive cloud-scale workloads. You will work cross-functionally with CPU/Compute core architects, IP designers, performance modeling teams, and software/firmware engineers to deliver world-class silicon that powers the future of cloud computing and AI infrastructure.

### SoC Architecture Definition
- Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems.

### IP Selection & Integration
- Define requirements and drive decisions for third-party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves).

### PPA Optimization
- Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets.

### Advanced Packaging Strategy
- Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions.

### HW/SW Co-Design
- Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies.

### Performance Modeling
- Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks.

### Technical Leadership
- Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up phases. #LI-JK1

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 23, 2026
- Last checked: Oct 23, 2026
- Listed for: Under a day
- Location: HsinChu[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804002)

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### [<Data Center> Advanced Package Engineer/ Technical Manager](https://jobs.opennash.com/companies/mediatek/jobs/ab089883c9560ca336b2/)

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### [<Data Center> Datacenter Compute Accelerator Architect](https://jobs.opennash.com/companies/mediatek/jobs/5f7406dc0ba3f652825d/)

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### [<Data Center> Datacenter Compute SoC Performance Modeling Architect](https://jobs.opennash.com/companies/mediatek/jobs/4ba286edec93bde7df45/)

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### [<Data Center> Datacenter Server CPU Platform Architect](https://jobs.opennash.com/companies/mediatek/jobs/5b93ae4cbed7acc0f12d/)

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### [<Data Center> HBM IP Subsystem End-to-End Solution Leader](https://jobs.opennash.com/companies/mediatek/jobs/ff8d81b13a4a149c44fc/)

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