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MediaTek · Hefei

# SOC DFT Engineer

Hefei Operations 

Listed on MediaTek’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there.
[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MHF120240902001)

[OpenNash Jobs](https://jobs.opennash.com/) / [MediaTek](https://jobs.opennash.com/companies/mediatek/) / SOC DFT Engineer

## Job description
- Responsible for SOC chip-level and sub-system level DFT architecture definition, scan insertion, scan timing constraint, ATPG pattern generation/simulation, ATPG post-silicon diagnosis, MP support and etc.
- Support chip-level/sub-system DFT related check and implementation, including ATPG DRC, ATPG coverage improve, ATPG pattern count reduction, Equivalence check, Scan SDC constraint, Timing Sign-off, Timing ECO, Power Analysis, and other scan related performance/power/area quality boost, etc.
- Support SOC physical implementation for DFT part, and support TE for MP issue.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 23, 2026
- Last checked: Oct 23, 2026
- Listed for: Under a day
- Location: Hefei[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MHF120240902001)

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