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MediaTek · HsinChu

# <Data Center> Datacenter Compute Accelerator Architect

HsinChu Data & Analytics 

Listed on MediaTek’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there.
[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804005)

[OpenNash Jobs](https://jobs.opennash.com/) / [MediaTek](https://jobs.opennash.com/companies/mediatek/) / <Data Center> Datacenter Compute Accelerator Architect

## Job description

### Role Summary

We are seeking a highly specialized Datacenter Compute Accelerator Architect to lead the design and integration of dedicated hardware accelerators within our next-generation DC silicon. As datacenter workloads increasingly rely on heterogeneous computing, offloading critical functions (such as cryptography, data compression, networking, and memory movement) from the main CPU/compute cores is vital for maximizing system-level performance and efficiency.

In this role, you will define the architecture of these on-chip uncore accelerators and ensure they integrate seamlessly with the coherent interconnect, memory hierarchy, and hypervisor software stack. You will work at the intersection of hardware and software to deliver scalable, high-throughput, and low-latency acceleration solutions for hyper-scale cloud environments.

### Architecture Definition
- Define the microarchitecture and write detailed specifications for tightly-coupled uncore accelerators (e.g., Crypto/Security, Compression/Decompression, DMA engines, Tensor cores, Data Analytics offloads).

### SoC Integration
- Integrate accelerator blocks into the coherent interconnect (e.g., AMBA CHI, proprietary NoC) and memory subsystem. Manage data flows to ensure optimal latency and bandwidth utilization without starving CPU cores.

### HW/SW Co-Design
- Partner closely with kernel and driver engineers to define software programming models, APIs, and descriptor formats.

### Virtualization & Security
- Ensure accelerators support cloud-native environments by implementing robust virtualization (e.g., SR-IOV, PASID) and integrating with memory management units (SMMU/IOMMU) for secure, isolated execution.

### PPA & Performance Trade-offs
- Conduct rigorous Power, Performance, and Area (PPA) analysis. Work with performance modeling teams to simulate accelerator throughput and latency under heavy datacenter workloads.

### Execution Leadership
- Serve as the technical focal point during RTL implementation, verification, and silicon bring-up, ensuring the final silicon matches architectural intent. #LI-JK1

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 23, 2026
- Last checked: Oct 23, 2026
- Listed for: Under a day
- Location: HsinChu[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804005)

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### [<Data Center> Advanced Package Engineer/ Technical Manager](https://jobs.opennash.com/companies/mediatek/jobs/ab089883c9560ca336b2/)

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### [<Data Center> Datacenter Compute SoC Architect](https://jobs.opennash.com/companies/mediatek/jobs/bac14c72a698faecf738/)

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### [<Data Center> Datacenter Compute SoC Performance Modeling Architect](https://jobs.opennash.com/companies/mediatek/jobs/4ba286edec93bde7df45/)

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### [<Data Center> Datacenter Server CPU Platform Architect](https://jobs.opennash.com/companies/mediatek/jobs/5b93ae4cbed7acc0f12d/)

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### [<Data Center> HBM IP Subsystem End-to-End Solution Leader](https://jobs.opennash.com/companies/mediatek/jobs/ff8d81b13a4a149c44fc/)

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