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MediaTek · HsinChu

# <Data Center> Datacenter Compute SoC Performance Modeling Architect

HsinChu Data & Analytics 

Listed on MediaTek’s official careers site. Listed as of October 23, 2026. Check that it is still open and apply there.
[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804004)

[OpenNash Jobs](https://jobs.opennash.com/) / [MediaTek](https://jobs.opennash.com/companies/mediatek/) / <Data Center> Datacenter Compute SoC Performance Modeling Architect

## Job description

### Role Summary

We are looking for a highly skilled Datacenter Compute SoC Performance Modeling Engineer. In this role, you will be at the forefront of defining our next-generation cloud and datacenter processors. You will develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs, identify performance bottlenecks, and project system performance across a wide range of datacenter workloads.

You will collaborate closely with CPU/Compute core architects, SoC architects, IP architects, workload characterization teams, and RTL designers to ensure our silicon delivers industry-leading performance-per-watt and scales efficiently to meet the demands of modern hyper-scale infrastructure.

### Simulator Development
- Design, develop, and maintain cycle-accurate and transaction-level performance models (C++/SystemC) for multi-core datacenter SoCs, including CPU cores, memory subsystems, interconnects (NoC), and high-speed I/O (PCIe/CXL).

### Workload Analysis & Profiling
- Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines to drive architectural requirements.

### Performance Exploration
- Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts.

### Bottleneck Identification
- Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions.

### RTL & Silicon Correlation
- Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon, ensuring model accuracy.

### Tooling & Infrastructure
- Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis libraries. #LI-JK1

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 23, 2026
- Last checked: Oct 23, 2026
- Listed for: Under a day
- Location: HsinChu[Apply on MediaTek’s careers site →](https://careers.mediatek.com/en/jobs/MTK120260804004)

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### [<Data Center> Advanced Package Engineer/ Technical Manager](https://jobs.opennash.com/companies/mediatek/jobs/ab089883c9560ca336b2/)

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### [<Data Center> Datacenter Compute Accelerator Architect](https://jobs.opennash.com/companies/mediatek/jobs/5f7406dc0ba3f652825d/)

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### [<Data Center> Datacenter Compute SoC Architect](https://jobs.opennash.com/companies/mediatek/jobs/bac14c72a698faecf738/)

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### [<Data Center> Datacenter Server CPU Platform Architect](https://jobs.opennash.com/companies/mediatek/jobs/5b93ae4cbed7acc0f12d/)

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### [<Data Center> HBM IP Subsystem End-to-End Solution Leader](https://jobs.opennash.com/companies/mediatek/jobs/ff8d81b13a4a149c44fc/)

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