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Marvell Technology · Bangalore

# Advanced Package Architect Sr. Staff Engineer

Bangalore Senior individual contributor Operations 

Listed on Marvell Technology’s official careers site. Posted October 22, 2026. Check that it is still open and apply there.
[Apply on Marvell Technology’s careers site →](https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Advanced-Package-Architect-Sr-Staff-Engineer_2605053)

[OpenNash Jobs](https://jobs.opennash.com/) / [Marvell Technology](https://jobs.opennash.com/companies/marvell-technology/) / Advanced Package Architect Sr. Staff Engineer

## Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Your Team, Your Impact Within this ecosystem, Marvell’s central advanced packaging organization plays a critical role in delivering next generation connectivity and compute products. The organization brings deep expertise in architecture, package design, and electrical performance, including SI/PI to develop advanced IC packages that support high speed interfaces.

This work directly shapes product performance, reliability, and time to market, making it a key contributor to Marvell’s overall technology leadership. What You Can Expect What You Can Expect Marvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages. The engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.

Key responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package‑level connectivity. The engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.

### What We're Looking For

8+ years of related professional experience. Previous experience developing netlists and schematics for large, complex packages. Previous experience developing C4 and BGA ball maps for high‑pin‑count designs. Proficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent Strong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization across package and system requirements.

Solid grasp of SI/PI fundamentals at the substrate, board, and system levels; familiarity with running and interpreting signal and power simulations is a plus. Knowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS‑S/R/L, EMIB, CPO, and CPC. High‑level understanding of thermal and mechanical package constraints (e.g., warpage, TIM). Experience contributing to tool, process, and flow development, including library maintenance and basic scripting for automation.

Familiarity with foundry design rules and substrate manufacturing constraints. Demonstrated ability to work across cross‑functional teams and global time zones; strong interpersonal skills and willingness to learn. Experience collaborating with chip and board design and electrical simulation teams to optimize package and system co‑design. Experience collaborating with chip and board design, and electrical simulation teams for co‑design and optimization.

Strong communication, presentation, and documentation skills. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.

We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.

Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S.

Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-CP1

## At a glance
- Posted by the employer: Oct 22, 2026
- First seen by OpenNash: Oct 24, 2026
- Last checked: Oct 31, 2026
- Listed for: 9 days
- Location: Bangalore[Apply on Marvell Technology’s careers site →](https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Advanced-Package-Architect-Sr-Staff-Engineer_2605053)

## Hiring at Marvell Technology
- Open jobs: 344
- New in the last 7 days: After two weekly collections
- Tracked since: Jul 10, 2026

[All Marvell Technology jobs](https://jobs.opennash.com/companies/marvell-technology/) · [Weekly hiring report](/reports/hiring/)

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