[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Intel · India, Bangalore # Silicon Packaging Design Engineer India, Bangalore Full-time Design Listed on Intel’s official careers site. Posted October 26, 2026. Check that it is still open and apply there. [Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Packaging-Design-Engineer_JR0288608) [OpenNash Jobs](https://jobs.opennash.com/) / [Intel](https://jobs.opennash.com/companies/intel/) / Silicon Packaging Design Engineer ## Job description ### Job Details Job Description: Define packaging solutions for highly innovative integrated circuits, meeting adequate mechanical, thermal and electrical performance with the goal to achieve lowest package and system level cost. Co-design with chip designer, system engineering and PCB design teams during the development stage to optimize pad layout and pin map for most cost effective package and system. Independently plan, design and develop quality custom lead frame/substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues of the device. Technical lead for implementing packaging solutions at OSAT assembly site and/or internal assembly site. Ensure optimized package design which meets the assembly design rules of the selected assembly site. Work with the assembly partner to mitigate any potential risk and improve situation to meet yield target within the project milestone requirement. Co-work with NPI manager to prepare assembly site readiness for continuous uninterrupted flow from wafer fab-out to quality packaged sample meeting the required NPI schedule. Maintain complete set of product specific packaging related drawings, and reports. ### Qualifications Bachelor / Master degree in Electrical Engineering / Mechanical Engineering / Material Science with more than 10 years experience in the field of IC Packaging Design and Layout. Package design experience using Siemens Xpedition EDA tool set is a must. Understand performance and cost trade-offs for different layout and assembly rules. Extensive manufacturing process knowledge regarding wafer bumping, substrate and lead frame manufacturing and assembly of wire bond and flip chip packages is required. Practical knowledge of Signal integrity and Power integrity in PCB design will be an advantage. Possesses good analytical, communication and organization skills. ### Job Type Intel Contract Employee Shift: Shift 1 (India) ### Primary Location India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. - Job posting details (such as work model, location or time type) are subject to change. ### ADDITIONAL INFORMATION - Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. ## At a glance - Posted by the employer: Oct 26, 2026 - First seen by OpenNash: Nov 1, 2026 - Last checked: Nov 1, 2026 - Listed for: 6 days - Location: India, Bangalore - Employment type: Full-time[Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Packaging-Design-Engineer_JR0288608) ## Hiring at Intel - Open jobs: 801 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Intel jobs](https://jobs.opennash.com/companies/intel/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Intel ### [Analog Circuit Design Engineer](https://jobs.opennash.com/companies/intel/jobs/a5d0948219cb3844214f/) India, Bangalore ### [Analog Circuit Design Engineering Manager](https://jobs.opennash.com/companies/intel/jobs/0b086c10bf42e9b1b7d3/) India, Bangalore ### [Analog Design Engineer](https://jobs.opennash.com/companies/intel/jobs/f8af096f7a6fd31f2831/) India, Bangalore ## Similar jobs at other companies ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [Staff Physical Design Engineer - Custom Silicon Group](https://jobs.opennash.com/companies/qualcomm/jobs/fabbe4056864b0076098/) Qualcomm · Bangalore, India ### [Engineer, Packaging Engineering (Mechanical Design)](https://jobs.opennash.com/companies/sandisk/jobs/3be7542e5dddd27482bc/) Sandisk ### [Packaging Engineer (Substrate Design and Layout)](https://jobs.opennash.com/companies/sandisk/jobs/0879670410f04691dc62/) Sandisk ### [Manager, Silicon Circuit Co-Design — Silicon Co-Design Group](https://jobs.opennash.com/companies/nvidia/jobs/d10b9778d20e032db54d/) NVIDIA · China, Shanghai OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. [ OpenNash ](https://opennash.com/) AI-native services firm that builds custom software and 24/7 AI agents. OpenNash Jobs is an OpenNash Applied AI project. [Book time with OpenNash](https://calendly.com/opennash/new-meeting?hide_gdpr_banner=1) Jobs - [Search jobs](https://jobs.opennash.com/search/) - [Companies](https://jobs.opennash.com/explore/) - [Hiring report](https://jobs.opennash.com/reports/hiring/) - [AI assistants](https://jobs.opennash.com/connect/) - [How it works](https://jobs.opennash.com/methodology/) OpenNash - [opennash.com](https://opennash.com/) - [Services](https://opennash.com/ai-agent-consulting/) - [OpenNash CX](https://opennash.com/cx/) - [AI Tools](https://opennash.com/ai-tools/) - [Blog](https://opennash.com/blog/) - [About](https://opennash.com/about/) Contact - [hello@opennash.com](mailto:hello@opennash.com) - [LinkedIn](https://www.linkedin.com/company/opennash) - [Support](https://jobs.opennash.com/support/) - [Privacy](https://jobs.opennash.com/privacy/) - [Terms](https://jobs.opennash.com/terms/) © 2026 OpenNash, Inc. Company names and public job postings belong to their respective owners. Employers control source availability and application decisions.